J313 is the codename for the M1 MacBook Air. Saagar Jha
> On Apr 26, 2021, at 11:56, Georges Martin <jrjsm...@gmail.com> wrote: > >> Aha, hw.optional! That's useful, thanks Georges! > > You're welcome :-) You also have: > > hw.optional.amx_version: 2 > hw.optional.arm64: 1 > hw.targettype: J313 > > "amx" is the Neural Engine and I think "J313" is the code name for the M1. > > You may find this article very interesting: > > > https://levelup.gitconnected.com/armv9-what-is-the-big-deal-4528f20f78f3 > <https://levelup.gitconnected.com/armv9-what-is-the-big-deal-4528f20f78f3> > > It describes the new ARMv9 instruction set with SVE2 and how it compares to > Intel/AMD MMX/SSE/AVX and NEON/SVE. > > Question is: would Apple adopt ARMv9 with SVE2 in a M2 for a future Mac Pro ? > ;-) > > G. > >> Le 26 avr. 2021 à 20:44, Jason Liu <jason...@umich.edu >> <mailto:jason...@umich.edu>> a écrit : >> >> Aha, hw.optional! That's useful, thanks Georges! >> >> -- >> Jason Liu >> >> >> On Mon, Apr 26, 2021 at 2:16 PM Georges Martin <jrjsm...@gmail.com >> <mailto:jrjsm...@gmail.com>> wrote: >> $ sysctl hw.optional | grep -E 'neon|armv8' >> hw.optional.neon: 1 >> hw.optional.neon_hpfp: 1 >> hw.optional.neon_fp16: 1 >> hw.optional.armv8_1_atomics: 1 >> hw.optional.armv8_crc32: 1 >> hw.optional.armv8_2_fhm: 1 >> hw.optional.armv8_2_sha512: 1 >> hw.optional.armv8_2_sha3: 1 >> >>> Le 26 avr. 2021 à 19:55, Jason Liu <jason...@umich.edu >>> <mailto:jason...@umich.edu>> a écrit : >>> >>> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones <jon...@hep.phy.cam.ac.uk >>> <mailto:jon...@hep.phy.cam.ac.uk>> wrote: >>> Thats not at all surprising as those instruction sets are very much >>> specific to X86_64 systems. >>> >>> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. >>> Neon), but they are entirely different to those on X86_64 machines. >>> >>> Whether or these are supported on Apple’s M1 processors I have no idea. >>> >>> It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD >>> (which I guess is supposed to be similar to AVX?): >>> >>> https://discussions.apple.com/thread/252073619 >>> <https://discussions.apple.com/thread/252073619> >>> >>> -- >>> Jason Liu >>> >>> >>> On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones <jon...@hep.phy.cam.ac.uk >>> <mailto:jon...@hep.phy.cam.ac.uk>> wrote: >>> >>> >>>> On 26 Apr 2021, at 6:28 pm, Jason Liu <jason...@umich.edu >>>> <mailto:jason...@umich.edu>> wrote: >>>> >>>> Thanks Arno :) >>>> >>>> I'm kind of surprised that the M1 doesn't seem to support any SSE or >>>> AVX.... >>> >>> >>> Thats not at all surprising as those instruction sets are very much >>> specific to X86_64 systems. >>> >>> RISC processors, Arm, do have their own sets of SIMD instructions (e.g. >>> Neon), but they are entirely different to those on X86_64 machines. >>> >>> Whether or these are supported on Apple’s M1 processors I have no idea. >>> >>> Chris >>> >>> >>> >>>> >>>> Does "sysctl machdep.cpu.features" return anything? >>>> >>>> -- >>>> Jason Liu >>>> >>>> >>>> On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala <a...@alum.wpi.edu >>>> <mailto:a...@alum.wpi.edu>> wrote: >>>> > On 26 Apr 2021, at 13:20, Jason Liu <jason...@umich.edu >>>> > <mailto:jason...@umich.edu>> wrote: >>>> > >>>> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse” >>>> >>>> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse” >>>> machdep.cpu.brand_string: Apple M1 >>>> >>>> -- >>>> arno s hautala /-| a...@alum.wpi.edu <mailto:a...@alum.wpi.edu> >>>> >>>> pgp b2c9d448 >>>> >>>> >>> >> >
