/* * 0xc0000000 map to 0x40000000 */ LEAF(test) li a0, 0xc0000000 li a1, 0x40000000 bal CPU_TLBInit nop END(test) LEAF(CPU_TLBInit) li a3, 0 # First TLB index.
li a2, PG_SIZE_16M mtc0 a2, COP_0_TLB_PG_MASK # All pages are 16Mb. 1: and a2, a0, PG_SVPN ------------------------------- 这个地方是不是应该使用PG_HVPN? mtc0 a2, COP_0_TLB_HI # Set up entry high. move a2, a0 srl a2, a0, PG_SHIFT and a2, a2, PG_FRAME ori a2, PG_IOPAGE mtc0 a2, COP_0_TLB_LO0 # Set up entry low0. addu a2, (0x01000000 >> PG_SHIFT) mtc0 a2, COP_0_TLB_LO1 # Set up entry low1. mtc0 a3, COP_0_TLB_INDEX # Set the index. addiu a3, 1 li a2, 0x02000000 subu a1, a2 nop tlbwi # Write the TLB bgtz a1, 1b addu a0, a2 # Step address 32Mb. jr ra nop END(CPU_TLBInit) #define PG_SVPN 0xfffff000 /* Software page no mask */ #define PG_HVPN 0xffffe000 /* Hardware page no mask */ #define PG_ODDPG 0x00001000 /* Odd even pte entry */ #define PG_ASID 0x000000ff /* Address space ID */ #define PG_G 0x00000001 /* HW */ #define PG_V 0x00000002 #define PG_NV 0x00000000 #define PG_M 0x00000004 #define PG_ATTR 0x0000003f #define PG_UNCACHED 0x00000010 #define PG_CACHED 0x00000018 #define PG_CACHEMODE 0x00000038 #define PG_ROPAGE (PG_V | PG_RO | PG_CACHED) /* Write protected */ #define PG_RWPAGE (PG_V | PG_M | PG_CACHED) /* Not wr-prot not clean */ #define PG_CWPAGE (PG_V | PG_CACHED) /* Not wr-prot but clean */ #define PG_IOPAGE (PG_G | PG_V | PG_M | PG_UNCACHED) #define PG_FRAME 0x3fffffc0 #define PG_SHIFT 6 #define PG_SIZE_4K 0x00000000 #define PG_SIZE_16K 0x00006000 #define PG_SIZE_64K 0x0001e000 #define PG_SIZE_256K 0x0007e000 #define PG_SIZE_1M 0x001fe000 #define PG_SIZE_4M 0x007fe000 #define PG_SIZE_16M 0x01ffe000 -- You received this message because you are subscribed to the Google Groups "loongson-dev" group. To post to this group, send email to loongson-dev@googlegroups.com. To unsubscribe from this group, send email to loongson-dev+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/loongson-dev?hl=en.
