Thanks. Evan On Feb 16, 2008, at 6:46 AM, Andrew Lenharth wrote:
> Author: alenhar2 > Date: Sat Feb 16 08:46:26 2008 > New Revision: 47213 > > URL: http://llvm.org/viewvc/llvm-project?rev=47213&view=rev > Log: > I cannot find a libgcc function for this builtin. Therefor > expanding it to a noop (which is how it use to be treated). If > someone who knows the x86 backend better than me could tell me how > to get a lock prefix on an instruction, that would be nice to > complete x86 support. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/CBackend/CBackend.cpp > llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp > llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp > llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp > llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp > llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 16 > 08:46:26 2008 > @@ -1135,11 +1135,21 @@ > > case ISD::MEMBARRIER: { > assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); > - SDOperand Ops[6]; > - Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. > - for (int x = 1; x < 6; ++x) > - Ops[x] = PromoteOp(Node->getOperand(x)); > - Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); > + switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { > + default: assert(0 && "This action is not supported yet!"); > + case TargetLowering::Legal: { > + SDOperand Ops[6]; > + Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the > chain. > + for (int x = 1; x < 6; ++x) > + Ops[x] = PromoteOp(Node->getOperand(x)); > + Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); > + break; > + } > + case TargetLowering::Expand: > + //There is no libgcc call for this op > + Result = Node->getOperand(0); // Noop > + break; > + } > break; > } > > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Feb 16 > 08:46:26 2008 > @@ -210,6 +210,7 @@ > setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); > setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); > setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); > + setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); > > if (!Subtarget->hasV6Ops()) { > setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); > > Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) > +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Sat Feb 16 08:46:26 > 2008 > @@ -2459,6 +2459,7 @@ > if (Function *F = CI->getCalledFunction()) > switch (F->getIntrinsicID()) { > case Intrinsic::not_intrinsic: > + case Intrinsic::memory_barrier: > case Intrinsic::vastart: > case Intrinsic::vacopy: > case Intrinsic::vaend: > @@ -2544,6 +2545,9 @@ > WroteCallee = true; > break; > } > + case Intrinsic::memory_barrier: > + Out << "0; __sync_syncronize()"; > + return; > case Intrinsic::vastart: > Out << "0; "; > > > Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Sat Feb 16 > 08:46:26 2008 > @@ -181,7 +181,8 @@ > setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); > setOperationAction(ISD::MEMSET, MVT::Other, Expand); > setOperationAction(ISD::MEMCPY, MVT::Other, Expand); > - > + setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); > + > // PowerPC has no SREM/UREM instructions > setOperationAction(ISD::SREM, MVT::i32, Expand); > setOperationAction(ISD::UREM, MVT::i32, Expand); > > Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Sat Feb 16 > 08:46:26 2008 > @@ -69,7 +69,8 @@ > setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); > setOperationAction(ISD::MEMSET , MVT::Other, Expand); > setOperationAction(ISD::MEMCPY , MVT::Other, Expand); > - > + setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); > + > setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); > setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); > > > Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sat Feb 16 > 08:46:26 2008 > @@ -84,6 +84,7 @@ > setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); > setOperationAction(ISD::MEMSET, MVT::Other, Expand); > setOperationAction(ISD::MEMCPY, MVT::Other, Expand); > + setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); > > setOperationAction(ISD::CTPOP, MVT::i32, Expand); > setOperationAction(ISD::CTTZ , MVT::i32, Expand); > > Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sat Feb 16 > 08:46:26 2008 > @@ -81,7 +81,8 @@ > setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); > setOperationAction(ISD::MEMSET, MVT::Other, Expand); > setOperationAction(ISD::MEMCPY, MVT::Other, Expand); > - > + setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); > + > // PowerPC has no SREM/UREM instructions > setOperationAction(ISD::SREM, MVT::i32, Expand); > setOperationAction(ISD::UREM, MVT::i32, Expand); > > Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sat Feb 16 > 08:46:26 2008 > @@ -195,7 +195,8 @@ > setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); > setOperationAction(ISD::MEMSET, MVT::Other, Expand); > setOperationAction(ISD::MEMCPY, MVT::Other, Expand); > - > + setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); > + > setOperationAction(ISD::FSIN , MVT::f64, Expand); > setOperationAction(ISD::FCOS , MVT::f64, Expand); > setOperationAction(ISD::FREM , MVT::f64, Expand); > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47213&r1=47212&r2=47213&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Feb 16 > 08:46:26 2008 > @@ -281,6 +281,10 @@ > setOperationAction(ISD::MEMSET , MVT::Other, Custom); > setOperationAction(ISD::MEMCPY , MVT::Other, Custom); > > + if (!Subtarget->hasSSE2()) > + setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); > + > + > // Use the default ISD::LOCATION, ISD::DECLARE expansion. > setOperationAction(ISD::LOCATION, MVT::Other, Expand); > // FIXME - use subtarget debug flags > > > _______________________________________________ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
