Author: evancheng
Date: Wed Jan 23 17:17:41 2008
New Revision: 46286
URL: http://llvm.org/viewvc/llvm-project?rev=46286&view=rev
Log:
Let each target decide byval alignment. For X86, it's 4-byte unless the
aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the
type.
Added:
llvm/trunk/test/CodeGen/X86/byval6.ll
llvm/trunk/test/CodeGen/X86/byval7.ll
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/test/CodeGen/X86/byval4.ll
llvm/trunk/test/CodeGen/X86/byval5.ll
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=46286&r1=46285&r2=46286&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jan 23 17:17:41 2008
@@ -405,6 +405,10 @@
return VT == MVT::iPTR ? PointerTy : VT;
}
+ /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
+ /// function arguments in the caller parameter area.
+ virtual unsigned getByValTypeAlignment(const Type *Ty) const;
+
/// getRegisterType - Return the type of registers that this ValueType will
/// eventually require.
MVT::ValueType getRegisterType(MVT::ValueType VT) const {
@@ -433,7 +437,7 @@
}
assert(0 && "Unsupported extended type!");
}
-
+
/// hasTargetDAGCombine - If true, the target has custom DAG combine
/// transformations that it can perform for the specified node.
bool hasTargetDAGCombine(ISD::NodeType NT) const {
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46286&r1=46285&r2=46286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jan 23 17:17:41 2008
@@ -672,6 +672,46 @@
allowUnalignedMemoryAccesses = true; // x86 supports it!
}
+/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
+/// the desired ByVal argument alignment.
+static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
+ if (MaxAlign == 16)
+ return;
+ if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
+ if (VTy->getBitWidth() == 128)
+ MaxAlign = 16;
+ else if (VTy->getBitWidth() == 64)
+ if (MaxAlign < 8)
+ MaxAlign = 8;
+ } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
+ unsigned EltAlign = 0;
+ getMaxByValAlign(ATy->getElementType(), EltAlign);
+ if (EltAlign > MaxAlign)
+ MaxAlign = EltAlign;
+ } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
+ for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
+ unsigned EltAlign = 0;
+ getMaxByValAlign(STy->getElementType(i), EltAlign);
+ if (EltAlign > MaxAlign)
+ MaxAlign = EltAlign;
+ if (MaxAlign == 16)
+ break;
+ }
+ }
+ return;
+}
+
+/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
+/// function arguments in the caller parameter area. For X86, aggregates
+/// that contains are placed at 16-byte boundaries while the rest are at
+/// 4-byte boundaries.
+unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
+ if (Subtarget->is64Bit())
+ return getTargetData()->getABITypeAlignment(Ty);
+ unsigned Align = 4;
+ getMaxByValAlign(Ty, Align);
+ return Align;
+}
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
/// jumptable.
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=46286&r1=46285&r2=46286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jan 23 17:17:41 2008
@@ -322,6 +322,12 @@
/// getStackPtrReg - Return the stack pointer register we are using: either
/// ESP or RSP.
unsigned getStackPtrReg() const { return X86StackPtr; }
+
+ /// getByValTypeAlignment - Return the desired alignment for ByVal
aggregate
+ /// function arguments in the caller parameter area. For X86, aggregates
+ /// that contains are placed at 16-byte boundaries while the rest are at
+ /// 4-byte boundaries.
+ virtual unsigned getByValTypeAlignment(const Type *Ty) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
Modified: llvm/trunk/test/CodeGen/X86/byval4.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval4.ll?rev=46286&r1=46285&r2=46286&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/byval4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/byval4.ll Wed Jan 23 17:17:41 2008
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsw | count 2
+; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsw | count 2
+; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
%struct.s = type { i16, i16, i16, i16, i16, i16 }
Modified: llvm/trunk/test/CodeGen/X86/byval5.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval5.ll?rev=46286&r1=46285&r2=46286&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/byval5.ll (original)
+++ llvm/trunk/test/CodeGen/X86/byval5.ll Wed Jan 23 17:17:41 2008
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsb | count 2
+; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsb | count 2
+; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
%struct.s = type { i8, i8, i8, i8, i8, i8 }
Added: llvm/trunk/test/CodeGen/X86/byval6.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval6.ll?rev=46286&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/byval6.ll (added)
+++ llvm/trunk/test/CodeGen/X86/byval6.ll Wed Jan 23 17:17:41 2008
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep add | not grep 16
+
+ %struct.W = type { x86_fp80, x86_fp80 }
[EMAIL PROTECTED] = global %struct.W { x86_fp80 0xK4001A000000000000000,
x86_fp80 0xK4001C000000000000000 }, align 32
[EMAIL PROTECTED] = internal constant %struct.W { x86_fp80
0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 }
+
+define i32 @main() nounwind {
+entry:
+ tail call void (i32, ...)* @bar( i32 3, %struct.W* byval @.cpx )
nounwind
+ tail call void (i32, ...)* @baz( i32 3, %struct.W* byval @B ) nounwind
+ ret i32 undef
+}
+
+declare void @bar(i32, ...)
+
+declare void @baz(i32, ...)
Added: llvm/trunk/test/CodeGen/X86/byval7.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval7.ll?rev=46286&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/byval7.ll (added)
+++ llvm/trunk/test/CodeGen/X86/byval7.ll Wed Jan 23 17:17:41 2008
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep add | grep 16
+
+ %struct.S = type { <2 x i64> }
+
+define i32 @main() nounwind {
+entry:
+ %s = alloca %struct.S ; <%struct.S*> [#uses=2]
+ %tmp15 = getelementptr %struct.S* %s, i32 0, i32 0 ; <<2 x
i64>*> [#uses=1]
+ store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16
+ call void @t( i32 1, %struct.S* byval %s ) nounwind
+ ret i32 0
+}
+
+declare void @t(i32, %struct.S* byval )
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