Author: johannes
Date: Sat Jan 19 19:18:38 2008
New Revision: 46195
URL: http://llvm.org/viewvc/llvm-project?rev=46195&view=rev
Log:
Do not generate a FP_ROUND of f64 to f64.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46195&r1=46194&r2=46195&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jan 19 19:18:38 2008
@@ -3608,10 +3608,11 @@
MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
if (SrcVT == MVT::ppcf128) {
- SDOperand Lo, Hi;
- ExpandOp(Node->getOperand(0), Lo, Hi);
+ SDOperand Lo;
+ ExpandOp(Node->getOperand(0), Lo, Result);
// Round it the rest of the way (e.g. to f32) if needed.
- Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi, Op.getOperand(1));
+ if (DstVT!=MVT::f64)
+ Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
break;
}
// The only other way we can lower this is to turn it into a STORE,
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
