Author: lattner
Date: Wed Jan 9 23:45:39 2008
New Revision: 45824
URL: http://llvm.org/viewvc/llvm-project?rev=45824&view=rev
Log:
remove explicit sets of 'neverHasSideEffects' that can now be
inferred from the instr patterns.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrFPStack.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=45824&r1=45823&r2=45824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed Jan 9 23:45:39 2008
@@ -695,7 +695,7 @@
"subfic $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
-let isReMaterializable = 1, neverHasSideEffects = 1 in {
+let isReMaterializable = 1 in {
def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
"li $rD, $imm", IntGeneral,
[(set GPRC:$rD, immSExt16:$imm)]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=45824&r1=45823&r2=45824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Wed Jan 9 23:45:39 2008
@@ -466,7 +466,7 @@
def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
// Floating point constant loads.
-let isReMaterializable = 1, neverHasSideEffects = 1 in {
+let isReMaterializable = 1 in {
def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
[(set RFP32:$dst, fpimm0)]>;
def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=45824&r1=45823&r2=45824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Jan 9 23:45:39 2008
@@ -566,7 +566,7 @@
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>;
-let isReMaterializable = 1, neverHasSideEffects = 1 in {
+let isReMaterializable = 1 in {
def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
"mov{b}\t{$src, $dst|$dst, $src}",
[(set GR8:$dst, imm:$src)]>;
@@ -2466,7 +2466,7 @@
// Alias instructions that map movr0 to xor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let Defs = [EFLAGS], isReMaterializable = 1, neverHasSideEffects = 1 in {
+let Defs = [EFLAGS], isReMaterializable = 1 in {
def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
"xor{b}\t$dst, $dst",
[(set GR8:$dst, 0)]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=45824&r1=45823&r2=45824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jan 9 23:45:39 2008
@@ -487,7 +487,7 @@
//===----------------------------------------------------------------------===//
// Alias instructions that map zero vector to pxor.
-let isReMaterializable = 1, neverHasSideEffects = 1 in {
+let isReMaterializable = 1 in {
def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
"pxor\t$dst, $dst",
[(set VR64:$dst, (v2i32 immAllZerosV))]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=45824&r1=45823&r2=45824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jan 9 23:45:39 2008
@@ -445,7 +445,7 @@
// start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
-let isReMaterializable = 1, neverHasSideEffects = 1 in
+let isReMaterializable = 1 in
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
"pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB, OpSize;
@@ -940,7 +940,7 @@
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
// Alias instructions that map zero vector to pxor / xorp* for sse.
-let isReMaterializable = 1, neverHasSideEffects = 1 in
+let isReMaterializable = 1 in
def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
"xorps\t$dst, $dst",
[(set VR128:$dst, (v4i32 immAllZerosV))]>;
@@ -1141,7 +1141,7 @@
// start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
-let isReMaterializable = 1, neverHasSideEffects = 1 in
+let isReMaterializable = 1 in
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
"pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
Requires<[HasSSE2]>, TB, OpSize;
@@ -2119,7 +2119,7 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
-let isReMaterializable = 1, neverHasSideEffects = 1 in
+let isReMaterializable = 1 in
def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
"pcmpeqd\t$dst, $dst",
[(set VR128:$dst, (v4i32 immAllOnesV))]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=45824&r1=45823&r2=45824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Wed Jan 9 23:45:39 2008
@@ -201,7 +201,7 @@
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>;
-let isReMaterializable = 1, neverHasSideEffects = 1 in {
+let isReMaterializable = 1 in {
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
"movabs{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, imm:$src)]>;
@@ -1105,14 +1105,13 @@
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
// FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32.
Remove
// when we have a better way to specify isel priority.
-let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1,
- neverHasSideEffects = 1 in
+let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in
def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
"xor{l}\t${dst:subreg32}, ${dst:subreg32}",
[(set GR64:$dst, 0)]>;
// Materialize i64 constant where top 32-bits are zero.
-let AddedComplexity = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
+let AddedComplexity = 1, isReMaterializable = 1 in
def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins
i64i32imm:$src),
"mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32},
$src}",
[(set GR64:$dst, i64immZExt32:$src)]>;
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