Author: evancheng
Date: Wed Jan 9 17:01:55 2008
New Revision: 45787
URL: http://llvm.org/viewvc/llvm-project?rev=45787&view=rev
Log:
Special copy SUnit's do not have SDNode's.
Added:
llvm/trunk/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=45787&r1=45786&r2=45787&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Jan 9
17:01:55 2008
@@ -1208,13 +1208,13 @@
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
if (I->isCtrl) continue; // ignore chain preds
- if (I->Dep->Node->getOpcode() != ISD::CopyFromReg)
+ if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
Scratches++;
}
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->isCtrl) continue; // ignore chain succs
- if (I->Dep->Node->getOpcode() != ISD::CopyToReg)
+ if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
Scratches += 10;
}
return Scratches;
Added: llvm/trunk/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll?rev=45787&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll Wed Jan 9
17:01:55 2008
@@ -0,0 +1,32 @@
+; RUN: llvm-as < %s | llc -march=x86
+
+ %struct.indexentry = type { i32, i8*, i8*, i8*, i8*, i8* }
+
+define i32 @_bfd_stab_section_find_nearest_line(i32 %offset) nounwind {
+entry:
+ %tmp910 = add i32 0, %offset ; <i32> [#uses=1]
+ br i1 true, label %bb951, label %bb917
+
+bb917: ; preds = %entry
+ ret i32 0
+
+bb951: ; preds = %bb986, %entry
+ %tmp955 = sdiv i32 0, 2 ; <i32> [#uses=3]
+ %tmp961 = getelementptr %struct.indexentry* null, i32 %tmp955, i32 0
; <i32*> [#uses=1]
+ br i1 true, label %bb986, label %bb967
+
+bb967: ; preds = %bb951
+ ret i32 0
+
+bb986: ; preds = %bb951
+ %tmp993 = load i32* %tmp961, align 4 ; <i32> [#uses=1]
+ %tmp995 = icmp ugt i32 %tmp993, %tmp910 ; <i1> [#uses=2]
+ %tmp1002 = add i32 %tmp955, 1 ; <i32> [#uses=1]
+ %low.0 = select i1 %tmp995, i32 0, i32 %tmp1002 ; <i32>
[#uses=1]
+ %high.0 = select i1 %tmp995, i32 %tmp955, i32 0 ; <i32>
[#uses=1]
+ %tmp1006 = icmp eq i32 %low.0, %high.0 ; <i1> [#uses=1]
+ br i1 %tmp1006, label %UnifiedReturnBlock, label %bb951
+
+UnifiedReturnBlock: ; preds = %bb986
+ ret i32 1
+}
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