Author: evancheng
Date: Mon Jan 7 17:56:57 2008
New Revision: 45727
URL: http://llvm.org/viewvc/llvm-project?rev=45727&view=rev
Log:
Only mark instructions that load a single value without extension as
isSimpleLoad = 1.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45727&r1=45726&r2=45727&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Jan 7 17:56:57 2008
@@ -202,7 +202,7 @@
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
const TargetInstrDesc &TID = MI->getDesc();
unsigned NumOps = TID.getNumOperands();
- bool isLoad = TID.isSimpleLoad();
+ bool isLoad = !TID.mayStore();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
const MachineOperand &Offset = MI->getOperand(NumOps-3);
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=45727&r1=45726&r2=45727&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jan 7 17:56:57 2008
@@ -684,7 +684,8 @@
Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
-let isSimpleLoad = 1, AddedComplexity = 10 in {
+let AddedComplexity = 10 in {
+let isSimpleLoad = 1 in
def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
@@ -738,7 +739,7 @@
// FIXME: remove when we have a way to marking a MI with these properties.
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
-let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
+let isReturn = 1, isTerminator = 1 in
def LDM_RET : AXI4<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1,
variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
@@ -802,13 +803,13 @@
//
// Load
-let isSimpleLoad = 1 in {
+let isSimpleLoad = 1 in
def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr",
[(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
+let isSimpleLoad = 1, isReMaterializable = 1 in
def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr", []>;
@@ -875,7 +876,6 @@
def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb",
[]>;
-} // isSimpleLoad
// Store
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
@@ -939,7 +939,6 @@
//
// FIXME: $dst1 should be a def.
-let isSimpleLoad = 1 in
def LDM : AXI4<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=45727&r1=45726&r2=45727&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Jan 7 17:56:57 2008
@@ -188,7 +188,7 @@
}
// FIXME: remove when we have a way to marking a MI with these properties.
-let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
+let isReturn = 1, isTerminator = 1 in
def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
@@ -237,7 +237,7 @@
// Load Store Instructions.
//
-let isSimpleLoad = 1 in {
+let isSimpleLoad = 1 in
def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
@@ -258,25 +258,27 @@
"ldrsh $dst, $addr",
[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
+let isSimpleLoad = 1 in
def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
// Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
+let isSimpleLoad = 1 in
def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
"ldr $dst, $addr", []>;
// Load tconstpool
+let isSimpleLoad = 1 in
def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
+let isSimpleLoad = 1, isReMaterializable = 1 in
def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr", []>;
-} // isSimpleLoad
def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
@@ -307,7 +309,6 @@
// TODO: A7-44: LDMIA - load multiple
-let isSimpleLoad = 1 in
def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=45727&r1=45726&r2=45727&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Jan 7 17:56:57 2008
@@ -110,7 +110,6 @@
// Load / store multiple Instructions.
//
-let isSimpleLoad = 1 in {
def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
variable_ops),
"fldm${addr:submode}d${p} ${addr:base}, $dst1",
@@ -120,7 +119,6 @@
variable_ops),
"fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>;
-} // isSimpleLoad
let mayStore = 1 in {
def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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