Author: void
Date: Mon Jan 7 02:05:29 2008
New Revision: 45699
URL: http://llvm.org/viewvc/llvm-project?rev=45699&view=rev
Log:
Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45699&r1=45698&r2=45699&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jan 7 02:05:29 2008
@@ -771,19 +771,15 @@
switch (MI->getOpcode()) {
default: break;
case X86::MOV32rm:
- if (MI->getOperand(1).isRegister()) {
- unsigned Reg = MI->getOperand(1).getReg();
- const X86Subtarget &ST = TM.getSubtarget<X86Subtarget>();
-
- // Loads from stubs of global addresses are side effect free.
- if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
- MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
- MI->getOperand(4).isGlobal() &&
- ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM, false) &&
- MI->getOperand(2).getImm() == 1 &&
- MI->getOperand(3).getReg() == 0)
- return true;
- }
+ // Loads from stubs of global addresses are side effect free.
+ if (MI->getOperand(1).isReg() &&
+ MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
+ MI->getOperand(4).isGlobal() &&
+ TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad
+ (MI->getOperand(4).getGlobal(), TM, false) &&
+ MI->getOperand(2).getImm() == 1 &&
+ MI->getOperand(3).getReg() == 0)
+ return true;
// FALLTHROUGH
case X86::MOV8rm:
case X86::MOV16rm:
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