On Jan 4, 2008, at 10:49 PM, Evan Cheng wrote: > > On Jan 4, 2008, at 9:19 PM, Chris Lattner wrote: > >> Author: lattner >> Date: Fri Jan 4 23:19:56 2008 >> New Revision: 45620 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=45620&view=rev >> Log: >> factor some code better to avoid redundancy between >> isReallySideEffectFree and isReallyTriviallyReMaterializable. Why >> is a load from >> a global considered side-effect-free but not rematable? > > No reason they should be different. I just haven't move remat over.
They really can't be right now, for a gross reason. The issue is that "isrematable" always returns true except in a few cases. issideeffectfree returns false except in a few cases... > Although, isReallySideEffectFree looks wrong. How is this checked? I agree, this looks bogus or scary to me. -Chris > > > // Loads from global addresses which aren't redefined in the > function are > // side effect free. > if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) && > MI->getOperand(2).isImmediate() && > MI->getOperand(3).isRegister() && > MI->getOperand(4).isGlobalAddress() && > MI->getOperand(2).getImm() == 1 && > MI->getOperand(3).getReg() == 0) > return true; > > Bill, how are you checking the Global address isn't redefined > anywhere else? > > Evan > >> >> Modified: >> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45620&r1=45619&r2=45620&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jan 4 23:19:56 >> 2008 >> @@ -135,11 +135,13 @@ >> case X86::MMX_MOVD64rm: >> case X86::MMX_MOVQ64rm: >> // Loads from constant pools are trivially rematerializable. >> - return MI->getOperand(1).isRegister() && MI- >> >getOperand(2).isImmediate() && >> - MI->getOperand(3).isRegister() && MI- >> >getOperand(4).isConstantPoolIndex() && >> - MI->getOperand(1).getReg() == 0 && >> - MI->getOperand(2).getImm() == 1 && >> - MI->getOperand(3).getReg() == 0; >> + if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && >> + MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() && >> + MI->getOperand(1).getReg() == 0 && >> + MI->getOperand(2).getImm() == 1 && >> + MI->getOperand(3).getReg() == 0) >> + return true; >> + return false; >> } >> // All other instructions marked M_REMATERIALIZABLE are always >> trivially >> // rematerializable. >> @@ -168,32 +170,11 @@ >> MI->getOperand(3).getReg() == 0) >> return true; >> } >> - // FALLTHROUGH >> - case X86::MOV8rm: >> - case X86::MOV16rm: >> - case X86::MOV16_rm: >> - case X86::MOV32_rm: >> - case X86::MOV64rm: >> - case X86::LD_Fp64m: >> - case X86::MOVSSrm: >> - case X86::MOVSDrm: >> - case X86::MOVAPSrm: >> - case X86::MOVAPDrm: >> - case X86::MMX_MOVD64rm: >> - case X86::MMX_MOVQ64rm: >> - // Loads from constant pools have no side effects >> - return MI->getOperand(1).isRegister() && >> - MI->getOperand(2).isImmediate() && >> - MI->getOperand(3).isRegister() && >> - MI->getOperand(4).isConstantPoolIndex() && >> - MI->getOperand(1).getReg() == 0 && >> - MI->getOperand(2).getImm() == 1 && >> - MI->getOperand(3).getReg() == 0; >> + break; >> } >> >> - // All other instances of these instructions are presumed to >> have side >> - // effects. >> - return false; >> + // Anything that is rematerializable obviously has no side >> effects. >> + return isReallyTriviallyReMaterializable(MI); >> } >> >> /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. >> EFLAGS, that >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits@cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
