[llvm-commits] [llvm] r45622 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

[Chris Lattner]

Author: lattner
Date: Fri Jan  4 23:28:30 2008
New Revision: 45622

URL: http://llvm.org/viewvc/llvm-project?rev=45622&view=rev
Log:
simplify some code by using shorter accessors.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45622&r1=45621&r2=45622&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jan  4 23:28:30 2008
@@ -135,11 +135,13 @@
   case X86::MMX_MOVD64rm:
   case X86::MMX_MOVQ64rm:
     // Loads from constant pools are trivially rematerializable.
-    return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
-           MI->getOperand(3).isRegister() && 
MI->getOperand(4).isConstantPoolIndex() &&
-           MI->getOperand(1).getReg() == 0 &&
-           MI->getOperand(2).getImm() == 1 &&
-           MI->getOperand(3).getReg() == 0;
+    if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
+        MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
+        MI->getOperand(1).getReg() == 0 &&
+        MI->getOperand(2).getImm() == 1 &&
+        MI->getOperand(3).getReg() == 0)
+      return true;
+    return false;
   }
   // All other instructions marked M_REMATERIALIZABLE are always trivially
   // rematerializable.
@@ -161,10 +163,8 @@
       // Loads from global addresses which aren't redefined in the function are
       // side effect free.
       if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
-          MI->getOperand(2).isImmediate() &&
-          MI->getOperand(3).isRegister() &&
-          MI->getOperand(4).isGlobalAddress() &&
-          MI->getOperand(2).getImm() == 1 &&
+          MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
+          MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm() == 1 &&
           MI->getOperand(3).getReg() == 0)
         return true;
     }
@@ -181,14 +181,14 @@
   case X86::MOVAPDrm:
   case X86::MMX_MOVD64rm:
   case X86::MMX_MOVQ64rm:
-    // Loads from constant pools have no side effects
-    return MI->getOperand(1).isRegister() &&
-           MI->getOperand(2).isImmediate() &&
-           MI->getOperand(3).isRegister() &&
-           MI->getOperand(4).isConstantPoolIndex() &&
-           MI->getOperand(1).getReg() == 0 &&
-           MI->getOperand(2).getImm() == 1 &&
-           MI->getOperand(3).getReg() == 0;
+    // Loads from constant pools are trivially rematerializable.
+    if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
+        MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
+        MI->getOperand(1).getReg() == 0 &&
+        MI->getOperand(2).getImm() == 1 &&
+        MI->getOperand(3).getReg() == 0)
+      return true;
+    return false;
   }
 
   // All other instances of these instructions are presumed to have side


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