Author: resistor Date: Fri Jan 4 18:48:55 2008 New Revision: 45608 URL: http://llvm.org/viewvc/llvm-project?rev=45608&view=rev Log: I should not be allowed to commit when sleepy.
Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=45608&r1=45607&r2=45608&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Fri Jan 4 18:48:55 2008 @@ -249,7 +249,7 @@ // code into the entry block. MachineBasicBlock *MBB = Fn.begin(); MachineBasicBlock::iterator I = MBB->begin(); - if (!RegInfo->spillCalleeSavedRegisters(*MBB, I, CSI)) { + if (!TII.spillCalleeSavedRegisters(*MBB, I, CSI)) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. It's killed at the spill. MBB->addLiveIn(CSI[i].getReg()); @@ -280,7 +280,7 @@ // Restore all registers immediately before the return and any terminators // that preceed it. - if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) { + if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI)) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) { TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(), CSI[i].getFrameIdx(), _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits