Author: lattner Date: Sun Dec 30 17:40:31 2007 New Revision: 45465 URL: http://llvm.org/viewvc/llvm-project?rev=45465&view=rev Log: slightly simplify and document SSARegMap.
Modified: llvm/trunk/include/llvm/CodeGen/SSARegMap.h Modified: llvm/trunk/include/llvm/CodeGen/SSARegMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SSARegMap.h?rev=45465&r1=45464&r2=45465&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SSARegMap.h (original) +++ llvm/trunk/include/llvm/CodeGen/SSARegMap.h Sun Dec 30 17:40:31 2007 @@ -7,10 +7,7 @@ // //===----------------------------------------------------------------------===// // -// Map register numbers to register classes that are correctly sized (typed) to -// hold the information. Assists register allocation. Contained by -// MachineFunction, should be deleted by register allocator when it is no -// longer needed. +// This file defines the SSARegMap class. // //===----------------------------------------------------------------------===// @@ -18,21 +15,28 @@ #define LLVM_CODEGEN_SSAREGMAP_H #include "llvm/Target/MRegisterInfo.h" -#include "llvm/ADT/IndexedMap.h" +#include <vector> namespace llvm { - -class TargetRegisterClass; - + +/// SSARegMap - Keep track of information for each virtual register, including +/// its register class. class SSARegMap { - IndexedMap<const TargetRegisterClass*, VirtReg2IndexFunctor> RegClassMap; - unsigned NextRegNum; - - public: - SSARegMap() : NextRegNum(MRegisterInfo::FirstVirtualRegister) { } + /// VRegInfo - Information we keep for each virtual register. The entries in + /// this vector are actually converted to vreg numbers by adding the + /// MRegisterInfo::FirstVirtualRegister delta to their index. + std::vector<const TargetRegisterClass*> VRegInfo; + +public: + SSARegMap() { + VRegInfo.reserve(256); + } - const TargetRegisterClass* getRegClass(unsigned Reg) { - return RegClassMap[Reg]; + /// getRegClass - Return the register class of the specified virtual register. + const TargetRegisterClass *getRegClass(unsigned Reg) { + Reg -= MRegisterInfo::FirstVirtualRegister; + assert(Reg < VRegInfo.size() && "Invalid vreg!"); + return VRegInfo[Reg]; } /// createVirtualRegister - Create and return a new virtual register in the @@ -40,13 +44,14 @@ /// unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { assert(RegClass && "Cannot create register without RegClass!"); - RegClassMap.grow(NextRegNum); - RegClassMap[NextRegNum] = RegClass; - return NextRegNum++; + VRegInfo.push_back(RegClass); + return getLastVirtReg(); } + /// getLastVirtReg - Return the highest currently assigned virtual register. + /// unsigned getLastVirtReg() const { - return NextRegNum - 1; + return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1; } }; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits