Author: pingbak
Date: Wed Dec 19 01:35:06 2007
New Revision: 45196
URL: http://llvm.org/viewvc/llvm-project?rev=45196&view=rev
Log:
Add new immed16.ll test case, fix CellSPU errata to make test case work.
Added:
llvm/trunk/test/CodeGen/CellSPU/immed16.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=45196&r1=45195&r2=45196&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Wed Dec 19 01:35:06 2007
@@ -597,7 +597,7 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
- DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n");
+ DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
CurDAG->getTargetConstant(0, MVT::i32));
} else if (Opc == SPUISD::LDRESULT) {
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45196&r1=45195&r2=45196&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Dec 19 01:35:06 2007
@@ -670,6 +670,11 @@
SDOperand ptrOp;
int offset;
+ if (basep.getOpcode() == ISD::FrameIndex) {
+ // FrameIndex nodes are always properly aligned. Really.
+ return SDOperand();
+ }
+
if (basep.getOpcode() == ISD::ADD) {
const ConstantSDNode *CN =
cast<ConstantSDNode>(basep.Val->getOperand(1));
assert(CN != NULL
@@ -694,13 +699,10 @@
stVecVT = MVT::v16i8;
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
- // Realign the pointer as a D-Form address (ptrOp is the pointer,
- // to force a register load with the address; basep is the actual
- // dform addr offs($reg).
- ptrOp = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
- DAG.getConstant(0, PtrVT));
- basep = DAG.getNode(SPUISD::DFormAddr, PtrVT,
- ptrOp, DAG.getConstant((offset & ~0xf), PtrVT));
+ // Realign the pointer as a D-Form address (ptrOp is the pointer, basep is
+ // the actual dform addr offs($reg).
+ basep = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
+ DAG.getConstant((offset & ~0xf), PtrVT));
// Create the 16-byte aligned vector load
SDOperand alignLoad =
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45196&r1=45195&r2=45196&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Wed Dec 19 01:35:06 2007
@@ -62,7 +62,6 @@
case SPU::AHIvec:
case SPU::AHIr16:
case SPU::AIvec:
- case SPU::AIr32:
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
@@ -74,6 +73,19 @@
return true;
}
break;
+ case SPU::AIr32:
+ assert(MI.getNumOperands() == 3 &&
+ "wrong number of operands to AIr32");
+ if (MI.getOperand(0).isRegister() &&
+ (MI.getOperand(1).isRegister() ||
+ MI.getOperand(1).isFrameIndex()) &&
+ (MI.getOperand(2).isImmediate() &&
+ MI.getOperand(2).getImmedValue() == 0)) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ break;
#if 0
case SPU::ORIf64:
case SPU::ORIf32:
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=45196&r1=45195&r2=45196&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Wed Dec 19 01:35:06 2007
@@ -3476,10 +3476,8 @@
// Force load of global address to a register. These forms show up in
// SPUISD::DFormAddr pseudo instructions:
-/*
def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>;
def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>;
- */
// Instrinsics:
include "CellSDKIntrinsics.td"
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=45196&r1=45195&r2=45196&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Wed Dec 19 01:35:06 2007
@@ -585,8 +585,6 @@
SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
RegScavenger *RS) const
{
- assert(SPAdj == 0 && "Unexpected SP adjacency == 0");
-
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
Added: llvm/trunk/test/CodeGen/CellSPU/immed16.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed16.ll?rev=45196&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/immed16.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/immed16.ll Wed Dec 19 01:35:06 2007
@@ -0,0 +1,38 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep "ilh" %t1.s | count 5
+
+define i16 @test_1() {
+ %x = alloca i16, align 16
+ store i16 419, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_2() {
+ %x = alloca i16, align 16
+ store i16 1023, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_3() {
+ %x = alloca i16, align 16
+ store i16 -1023, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_4() {
+ %x = alloca i16, align 16
+ store i16 32767, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_5() {
+ %x = alloca i16, align 16
+ store i16 -32768, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_6() {
+ ret i16 0
+}
+
+
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