Author: djg
Date: Fri Dec 14 09:10:00 2007
New Revision: 45030
URL: http://llvm.org/viewvc/llvm-project?rev=45030&view=rev
Log:
Fix Intel asm syntax for the bsr and bsf instructions.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=45030&r1=45029&r2=45030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Dec 14 09:10:00 2007
@@ -450,32 +450,32 @@
// Bit scan instructions.
let Defs = [EFLAGS] in {
def BSF16rr : I<0xBC, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
- "bsf{w}\t{$src, $dst||$dst, $src}",
+ "bsf{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
- "bsf{w}\t{$src, $dst||$dst, $src}",
+ "bsf{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
(implicit EFLAGS)]>, TB;
def BSF32rr : I<0xBC, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
- "bsf{l}\t{$src, $dst||$dst, $src}",
+ "bsf{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
- "bsf{l}\t{$src, $dst||$dst, $src}",
+ "bsf{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
(implicit EFLAGS)]>, TB;
def BSR16rr : I<0xBD, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
- "bsr{w}\t{$src, $dst||$dst, $src}",
+ "bsr{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
- "bsr{w}\t{$src, $dst||$dst, $src}",
+ "bsr{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
(implicit EFLAGS)]>, TB;
def BSR32rr : I<0xBD, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
- "bsr{l}\t{$src, $dst||$dst, $src}",
+ "bsr{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
- "bsr{l}\t{$src, $dst||$dst, $src}",
+ "bsr{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
(implicit EFLAGS)]>, TB;
} // Defs = [EFLAGS]
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=45030&r1=45029&r2=45030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Fri Dec 14 09:10:00 2007
@@ -170,17 +170,17 @@
// Bit scan instructions.
let Defs = [EFLAGS] in {
def BSF64rr : RI<0xBC, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
- "bsf{q}\t{$src, $dst||$dst, $src}",
+ "bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsf GR64:$src))]>, TB;
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
- "bsf{q}\t{$src, $dst||$dst, $src}",
+ "bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsf (loadi64 addr:$src)))]>, TB;
def BSR64rr : RI<0xBD, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
- "bsr{q}\t{$src, $dst||$dst, $src}",
+ "bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsr GR64:$src))]>, TB;
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
- "bsr{q}\t{$src, $dst||$dst, $src}",
+ "bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsr (loadi64 addr:$src)))]>, TB;
} // Defs = [EFLAGS]
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