>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 12 >> 16:21:26 2007 >> @@ -483,6 +483,12 @@ >> setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); >> setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); >> setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); >> + setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand); >> + setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand); >> + setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand); >> + setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand); >> + setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand); >> + setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand); >> } > > Hi Dan, > > How do you create these nodes with vector types (in C)? I don't think > the legalizer is capable of expanding these ops with vector types?
SelectionDAGLegalize::ExpandBitCount uses ISD::SRL when lowering ISD::CTPOP, so a vector CTPOP gets a vector SRL, for example. I noticed a bug with the way this works though; I'll fix that shortly. Also, in C, one could vectorize a[i] << b[i], though LLVM doesn't currently support that. The legalizer expands these by running SplitVectorOp and ScalarizeVectorOp as necessary, just as with other operations. Dan -- Dan Gohman, Cray Inc. _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
