On Dec 12, 2007, at 5:37 PM, Evan Cheng wrote: > > On Dec 12, 2007, at 5:07 PM, Chris Lattner wrote: > >> On Dec 12, 2007, at 3:12 PM, Evan Cheng wrote: >>> isLoad = false; >>> - if (tii_->isTriviallyReMaterializable(MI)) { >>> - isLoad = MI->getInstrDescriptor()->Flags & M_LOAD_FLAG; >>> + const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); >>> + if ((TID->Flags & M_IMPLICIT_DEF_FLAG) || >>> + tii_->isTriviallyReMaterializable(MI)) { >>> + isLoad = TID->Flags & M_LOAD_FLAG; >>> return true; >>> } >> >> Hi Evan, >> >> At one point were discussed eliminating >> TII::isTriviallyReMaterializable. The argument is that target >> implementations shouldn't have to know about algorithms, they should >> just describe properties of the target, and the algorithm should >> figure out if it can make the xform from that info. > > What do you mean? The targets don't know about the remat algorithm. > It's just the spiller making use of a some property of the > instructions.
Ok, you are talking about isTriviallyReMaterializable, not M_IMPLICIT_DEF_FLAG. Right now it is defined as this: bool isTriviallyReMaterializable(MachineInstr *MI) const { return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) && isReallyTriviallyReMaterializable(MI); } X86::isReallyTriviallyReMaterializable() is: ... case X86::MMX_MOVD64rm: case X86::MMX_MOVQ64rm: // Loads from constant pools are trivially rematerializable. return MI->getOperand(1).isRegister() && MI->getOperand (2).isImmediate() && MI->getOperand(3).isRegister() && MI->getOperand (4).isConstantPoolIndex() && MI->getOperand(1).getReg() == 0 && MI->getOperand(2).getImmedValue() == 1 && MI->getOperand(3).getReg() == 0; } The targets is only describing properties of the instruction because we are not able to describe addressing mode in a generic way. Seems like we are not too far off from your "pipe dream". :-) Evan > > Evan > >> >> Is this a pipe dream? :) >> >> -Chris >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits@cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits