Author: evancheng
Date: Wed Dec 12 00:45:40 2007
New Revision: 44921
URL: http://llvm.org/viewvc/llvm-project?rev=44921&view=rev
Log:
Lower a build_vector with all constants into a constpool load unless it can be
done with a move to low part.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/vec_return.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=44921&r1=44920&r2=44921&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 12 00:45:40 2007
@@ -3157,21 +3157,21 @@
unsigned NumZero = 0;
unsigned NumNonZero = 0;
unsigned NonZeros = 0;
- unsigned NumNonZeroImms = 0;
+ bool HasNonImms = false;
SmallSet<SDOperand, 8> Values;
for (unsigned i = 0; i < NumElems; ++i) {
SDOperand Elt = Op.getOperand(i);
- if (Elt.getOpcode() != ISD::UNDEF) {
- Values.insert(Elt);
- if (isZeroNode(Elt))
- NumZero++;
- else {
- NonZeros |= (1 << i);
- NumNonZero++;
- if (Elt.getOpcode() == ISD::Constant ||
- Elt.getOpcode() == ISD::ConstantFP)
- NumNonZeroImms++;
- }
+ if (Elt.getOpcode() == ISD::UNDEF)
+ continue;
+ Values.insert(Elt);
+ if (Elt.getOpcode() != ISD::Constant &&
+ Elt.getOpcode() != ISD::ConstantFP)
+ HasNonImms = true;
+ if (isZeroNode(Elt))
+ NumZero++;
+ else {
+ NonZeros |= (1 << i);
+ NumNonZero++;
}
}
@@ -3185,7 +3185,7 @@
return SDOperand();
// Special case for single non-zero element.
- if (NumNonZero == 1) {
+ if (NumNonZero == 1 && NumElems <= 4) {
unsigned Idx = CountTrailingZeros_32(NonZeros);
SDOperand Item = Op.getOperand(Idx);
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
@@ -3193,6 +3193,8 @@
// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
NumZero > 0, DAG);
+ else if (!HasNonImms) // Otherwise, it's better to do a constpool load.
+ return SDOperand();
if (EVTBits == 32) {
// Turn it into a shuffle of zero and zero-extended scalar to vector.
@@ -3212,7 +3214,7 @@
// A vector full of immediates; various special cases are already
// handled, so this is best done with a single constant-pool load.
- if (NumNonZero == NumNonZeroImms)
+ if (!HasNonImms)
return SDOperand();
// Let legalizer expand 2-wide build_vectors.
Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_return.ll?rev=44921&r1=44920&r2=44921&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_return.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_return.ll Wed Dec 12 00:45:40 2007
@@ -1,5 +1,12 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -mcpu=yonah
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xorps | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movaps | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shuf
-<2 x double> %test() {
- ret <2 x double> <double 0.0, double 0.0>
+define <2 x double> @test() {
+ ret <2 x double> zeroinitializer
+}
+
+define <4 x i32> @test2() nounwind {
+ ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 >
}
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