Author: evancheng
Date: Mon Dec 10 20:09:15 2007
New Revision: 44838
URL: http://llvm.org/viewvc/llvm-project?rev=44838&view=rev
Log:
Switch over to MachineLoopInfo.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=44838&r1=44837&r2=44838&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Mon Dec 10 20:09:15
2007
@@ -32,7 +32,7 @@
namespace llvm {
class LiveVariables;
- class LoopInfo;
+ class MachineLoopInfo;
class MRegisterInfo;
class SSARegMap;
class TargetInstrInfo;
@@ -231,7 +231,7 @@
/// the given interval.
std::vector<LiveInterval*>
addIntervalsForSpills(const LiveInterval& i,
- const LoopInfo *loopInfo, VirtRegMap& vrm);
+ const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
/// isReMaterializable - Returns true if every definition of MI of every
/// val# of the specified interval is re-materializable. Also returns true
@@ -321,7 +321,8 @@
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds,
- unsigned &NewVReg, bool &HasDef, bool &HasUse, const LoopInfo
*loopInfo,
+ unsigned &NewVReg, bool &HasDef, bool &HasUse,
+ const MachineLoopInfo *loopInfo,
std::map<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs);
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
@@ -329,7 +330,7 @@
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int
LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
- SmallVector<int, 4> &ReMatIds, const LoopInfo *loopInfo,
+ SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs,
std::map<unsigned,std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs,
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=44838&r1=44837&r2=44838&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Dec 10 20:09:15 2007
@@ -19,10 +19,10 @@
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "VirtRegMap.h"
#include "llvm/Value.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
@@ -765,7 +765,7 @@
const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds,
unsigned &NewVReg, bool &HasDef, bool &HasUse,
- const LoopInfo *loopInfo,
+ const MachineLoopInfo *loopInfo,
std::map<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs) {
bool CanFold = false;
@@ -962,7 +962,7 @@
VirtRegMap &vrm, SSARegMap *RegMap,
const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds,
- const LoopInfo *loopInfo,
+ const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs,
std::map<unsigned, std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs,
@@ -1119,7 +1119,7 @@
}
// Update spill weight.
- unsigned loopDepth = loopInfo->getLoopDepth(MBB->getBasicBlock());
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
nI.weight += getSpillWeight(HasDef, HasUse, loopDepth);
}
@@ -1158,7 +1158,7 @@
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li,
- const LoopInfo *loopInfo, VirtRegMap &vrm) {
+ const MachineLoopInfo *loopInfo, VirtRegMap &vrm) {
// Since this is called after the analysis is done we don't know if
// LiveVariables is available
lv_ = getAnalysisToUpdate<LiveVariables>();
Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=44838&r1=44837&r2=44838&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Mon Dec 10 20:09:15 2007
@@ -16,9 +16,9 @@
#include "PhysRegTracker.h"
#include "VirtRegMap.h"
#include "llvm/Function.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterCoalescer.h"
@@ -67,7 +67,7 @@
SSARegMap *regmap_;
BitVector allocatableRegs_;
LiveIntervals* li_;
- const LoopInfo *loopInfo;
+ const MachineLoopInfo *loopInfo;
/// handled_ - Intervals are added to the handled_ set in the order of
their
/// start value. This is uses for backtracking.
@@ -103,7 +103,7 @@
// Make sure PassManager knows which analyses to make available
// to coalescing and which analyses coalescing invalidates.
AU.addRequiredTransitive<RegisterCoalescer>();
- AU.addRequired<LoopInfo>();
+ AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -254,7 +254,7 @@
regmap_ = mf_->getSSARegMap();
allocatableRegs_ = mri_->getAllocatableSet(fn);
li_ = &getAnalysis<LiveIntervals>();
- loopInfo = &getAnalysis<LoopInfo>();
+ loopInfo = &getAnalysis<MachineLoopInfo>();
// We don't run the coalescer here because we have no reason to
// interact with it. If the coalescer requires interaction, it
Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=44838&r1=44837&r2=44838&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Dec 10 20:09:15 2007
@@ -17,10 +17,10 @@
#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/Value.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/RegisterCoalescer.h"
@@ -72,7 +72,7 @@
AU.addPreservedID(TwoAddressInstructionPassID);
AU.addRequired<LiveVariables>();
AU.addRequired<LiveIntervals>();
- AU.addRequired<LoopInfo>();
+ AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -207,11 +207,10 @@
bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
unsigned DstReg) {
MachineBasicBlock *MBB = CopyMI->getParent();
- const BasicBlock *BB = MBB->getBasicBlock();
- const Loop *L = loopInfo->getLoopFor(BB);
+ const MachineLoop *L = loopInfo->getLoopFor(MBB);
if (!L)
return false;
- if (BB != L->getLoopLatch())
+ if (MBB != L->getLoopLatch())
return false;
DstReg = rep(DstReg);
@@ -540,8 +539,7 @@
unsigned SrcReg, DstReg;
if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) &&
JoinedCopies.count(CopyMI) == 0) {
- unsigned LoopDepth =
- loopInfo->getLoopDepth(CopyMI->getParent()->getBasicBlock());
+ unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth,
isBackEdgeCopy(CopyMI, DstReg)));
}
@@ -1072,7 +1070,7 @@
std::vector<CopyRec> VirtCopies;
std::vector<CopyRec> PhysCopies;
- unsigned LoopDepth = loopInfo->getLoopDepth(MBB->getBasicBlock());
+ unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E;) {
MachineInstr *Inst = MII++;
@@ -1143,9 +1141,10 @@
// Join intervals in the function prolog first. We want to join physical
// registers with virtual registers before the intervals got too long.
std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
- for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I !=
E;++I)
- MBBs.push_back(std::make_pair(loopInfo->
- getLoopDepth(I->getBasicBlock()), I));
+ for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I !=
E;++I){
+ MachineBasicBlock *MBB = I;
+ MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
+ }
// Sort by loop depth.
std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
@@ -1380,7 +1379,7 @@
tii_ = tm_->getInstrInfo();
li_ = &getAnalysis<LiveIntervals>();
lv_ = &getAnalysis<LiveVariables>();
- loopInfo = &getAnalysis<LoopInfo>();
+ loopInfo = &getAnalysis<MachineLoopInfo>();
DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
<< "********** Function: "
@@ -1427,7 +1426,7 @@
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
MachineBasicBlock* mbb = mbbi;
- unsigned loopDepth = loopInfo->getLoopDepth(mbb->getBasicBlock());
+ unsigned loopDepth = loopInfo->getLoopDepth(mbb);
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ) {
Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=44838&r1=44837&r2=44838&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Mon Dec 10 20:09:15 2007
@@ -28,7 +28,7 @@
class MRegisterInfo;
class TargetInstrInfo;
class VirtRegMap;
- class LoopInfo;
+ class MachineLoopInfo;
/// CopyRec - Representation for copy instructions in coalescer queue.
///
@@ -84,7 +84,7 @@
const TargetInstrInfo* tii_;
LiveIntervals *li_;
LiveVariables *lv_;
- const LoopInfo* loopInfo;
+ const MachineLoopInfo* loopInfo;
BitVector allocatableRegs_;
DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
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