> URL: http://llvm.org/viewvc/llvm-project?rev=43535&view=rev > Log: > Make i64=expand_vector_elt(v2i64) work in 32-bit mode.
Testcase please :) -Chris > > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=43535&r1=43534&r2=43535&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 30 > 19:32:36 2007 > @@ -5299,6 +5299,11 @@ > #endif > assert(0 && "Do not know how to expand this operator!"); > abort(); > + case ISD::EXTRACT_VECTOR_ELT: > + assert(VT==MVT::i64 && "Do not know how to expand this > operator!"); > + // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. > + Lo = ExpandEXTRACT_VECTOR_ELT(Op); > + return ExpandOp(Lo, Lo, Hi); > case ISD::UNDEF: > NVT = TLI.getTypeToExpandTo(VT); > Lo = DAG.getNode(ISD::UNDEF, NVT); > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=43535&r1=43534&r2=43535&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Oct 30 > 19:32:36 2007 > @@ -608,7 +608,8 @@ > setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); > setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); > setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); > - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); > + if (Subtarget->is64Bit()) > + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, > Custom); > > // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to > v2i64. > for (unsigned VT = (unsigned)MVT::v16i8; VT != > (unsigned)MVT::v2i64; VT++) { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
