Author: lattner
Date: Fri Aug 24 19:47:38 2007
New Revision: 41384
URL: http://llvm.org/viewvc/llvm-project?rev=41384&view=rev
Log:
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Aug 24 19:47:38 2007
@@ -907,12 +907,11 @@
MVT::ValueType VT) const;
- /// isOperandValidForConstraint - Return the specified operand (possibly
- /// modified) if the specified SDOperand is valid for the specified target
- /// constraint letter, otherwise return null.
- virtual SDOperand
- isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
- SelectionDAG &DAG);
+ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+ /// vector. If it is invalid, don't add anything to Ops.
+ virtual void LowerAsmOperandForConstraint(SDOperand Op, char
ConstraintLetter,
+ std::vector<SDOperand> &Ops,
+ SelectionDAG &DAG);
//===--------------------------------------------------------------------===//
// Scheduler hooks
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Aug 24
19:47:38 2007
@@ -3623,20 +3623,20 @@
assert(!OpInfo.isIndirect &&
"Don't know how to handle indirect other inputs yet!");
- InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
-
OpInfo.ConstraintCode[0],
- DAG);
- if (!InOperandVal.Val) {
+ std::vector<SDOperand> Ops;
+ TLI.LowerAsmOperandForConstraint(InOperandVal,
OpInfo.ConstraintCode[0],
+ Ops, DAG);
+ if (Ops.empty()) {
cerr << "Invalid operand for inline asm constraint '"
<< OpInfo.ConstraintCode << "'!\n";
exit(1);
}
// Add information to the INLINEASM node to know about this input.
- unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
+ unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
TLI.getPointerTy()));
- AsmNodeOperands.push_back(InOperandVal);
+ AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
break;
} else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Aug 24 19:47:38
2007
@@ -1354,12 +1354,12 @@
return C_Unknown;
}
-/// isOperandValidForConstraint - Return the specified operand (possibly
-/// modified) if the specified SDOperand is valid for the specified target
-/// constraint letter, otherwise return null.
-SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
- char ConstraintLetter,
- SelectionDAG &DAG) {
+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+/// vector. If it is invalid, don't add anything to Ops.
+void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
+ char ConstraintLetter,
+ std::vector<SDOperand> &Ops,
+ SelectionDAG &DAG) {
switch (ConstraintLetter) {
default: break;
case 'i': // Simple Integer or Relocatable Constant
@@ -1390,19 +1390,21 @@
if (ConstraintLetter != 'n') {
int64_t Offs = GA->getOffset();
if (C) Offs += C->getValue();
- return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(),
- Offs);
+ Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
+ Op.getValueType(), Offs));
+ return;
}
}
if (C) { // just C, no GV.
// Simple constants are not allowed for 's'.
- if (ConstraintLetter != 's')
- return DAG.getTargetConstant(C->getValue(), Op.getValueType());
+ if (ConstraintLetter != 's') {
+ Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
+ return;
+ }
}
break;
}
}
- return SDOperand(0,0);
}
std::vector<unsigned> TargetLowering::
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Aug 24 19:47:38 2007
@@ -3338,9 +3338,12 @@
}
-// isOperandValidForConstraint
-SDOperand PPCTargetLowering::
-isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+/// vector. If it is invalid, don't add anything to Ops.
+void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
+
std::vector<SDOperand>&Ops,
+ SelectionDAG &DAG) {
+ SDOperand Result(0,0);
switch (Letter) {
default: break;
case 'I':
@@ -3352,46 +3355,51 @@
case 'O':
case 'P': {
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
- if (!CST) return SDOperand(0, 0); // Must be an immediate to match.
+ if (!CST) return; // Must be an immediate to match.
unsigned Value = CST->getValue();
switch (Letter) {
default: assert(0 && "Unknown constraint letter!");
case 'I': // "I" is a signed 16-bit constant.
if ((short)Value == (int)Value)
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
if ((short)Value == 0)
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
if ((Value >> 16) == 0)
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'M': // "M" is a constant that is greater than 31.
if (Value > 31)
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'N': // "N" is a positive constant that is an exact power of two.
if ((int)Value > 0 && isPowerOf2_32(Value))
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'O': // "O" is the constant zero.
if (Value == 0)
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
if ((short)-Value == (int)-Value)
- return DAG.getTargetConstant(Value, Op.getValueType());
+ Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
}
break;
}
}
+ if (Result.Val) {
+ Ops.push_back(Result);
+ return;
+ }
+
// Handle standard constraint letters.
- return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
+ TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
}
// isLegalAddressingMode - Return true if the addressing mode represented
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Fri Aug 24 19:47:38 2007
@@ -244,9 +244,14 @@
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
- SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
- SelectionDAG &DAG);
+ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+ /// vector. If it is invalid, don't add anything to Ops.
+ virtual void LowerAsmOperandForConstraint(SDOperand Op,
+ char ConstraintLetter,
+ std::vector<SDOperand> &Ops,
+ SelectionDAG &DAG);
+
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
virtual bool isLegalAddressingMode(const AddrMode &AM, const Type
*Ty)const;
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Aug 24 19:47:38 2007
@@ -5002,29 +5002,38 @@
return TargetLowering::getConstraintType(Constraint);
}
-/// isOperandValidForConstraint - Return the specified operand (possibly
-/// modified) if the specified SDOperand is valid for the specified target
-/// constraint letter, otherwise return null.
-SDOperand X86TargetLowering::
-isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+/// vector. If it is invalid, don't add anything to Ops.
+void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
+ char Constraint,
+
std::vector<SDOperand>&Ops,
+ SelectionDAG &DAG) {
+ SDOperand Result(0, 0);
+
switch (Constraint) {
default: break;
case 'I':
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
- if (C->getValue() <= 31)
- return DAG.getTargetConstant(C->getValue(), Op.getValueType());
+ if (C->getValue() <= 31) {
+ Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
+ break;
+ }
}
- return SDOperand(0,0);
+ return;
case 'N':
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
- if (C->getValue() <= 255)
- return DAG.getTargetConstant(C->getValue(), Op.getValueType());
+ if (C->getValue() <= 255) {
+ Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
+ break;
+ }
}
- return SDOperand(0,0);
+ return;
case 'i': {
// Literal immediates are always ok.
- if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op))
- return DAG.getTargetConstant(CST->getValue(), Op.getValueType());
+ if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
+ Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
+ break;
+ }
// If we are in non-pic codegen mode, we allow the address of a global
(with
// an optional displacement) to be used with 'i'.
@@ -5054,18 +5063,24 @@
// match.
if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
false))
- return SDOperand(0, 0);
+ return;
Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
Offset);
- return Op;
+ Result = Op;
+ break;
}
// Otherwise, not valid for this mode.
- return SDOperand(0, 0);
+ return;
}
}
- return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
+
+ if (Result.Val) {
+ Ops.push_back(Result);
+ return;
+ }
+ return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops,
DAG);
}
std::vector<unsigned> X86TargetLowering::
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=41384&r1=41383&r2=41384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Fri Aug 24 19:47:38 2007
@@ -330,11 +330,13 @@
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
- /// isOperandValidForConstraint - Return the specified operand (possibly
- /// modified) if the specified SDOperand is valid for the specified target
- /// constraint letter, otherwise return null.
- SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
- SelectionDAG &DAG);
+
+ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+ /// vector. If it is invalid, don't add anything to Ops.
+ virtual void LowerAsmOperandForConstraint(SDOperand Op,
+ char ConstraintLetter,
+ std::vector<SDOperand> &Ops,
+ SelectionDAG &DAG);
/// getRegForInlineAsmConstraint - Given a physical register constraint
/// (e.g. {edx}), return the register number and the register class for the
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