Author: bruno
Date: Fri Aug 17 21:18:07 2007
New Revision: 41159
URL: http://llvm.org/viewvc/llvm-project?rev=41159&view=rev
Log:
support for Schedule included on Mips.td
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=41159&r1=41158&r2=41159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Fri Aug 17 21:18:07 2007
@@ -6,58 +6,44 @@
// University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// This is the top level entry point for the Mips target.
+//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-// Target-independent interfaces which we are implementing
+// Target-independent interfaces
//===----------------------------------------------------------------------===//
include "../Target.td"
//===----------------------------------------------------------------------===//
-// Register File Description
+// Descriptions
//===----------------------------------------------------------------------===//
include "MipsRegisterInfo.td"
-
-//===----------------------------------------------------------------------===//
-// Subtarget features
-//===----------------------------------------------------------------------===//
-
-// TODO: dummy, needed to compile
-def FeatureCIX : SubtargetFeature<"r3000", "isR3000", "true",
- "Enable r3000 extentions">;
-
-//===----------------------------------------------------------------------===//
-// Instruction Description
-//===----------------------------------------------------------------------===//
-
+include "MipsSchedule.td"
include "MipsInstrInfo.td"
+include "MipsCallingConv.td"
def MipsInstrInfo : InstrInfo {
- // Define how we want to layout our target-specific information field.
let TSFlagsFields = [];
let TSFlagsShifts = [];
}
+
//===----------------------------------------------------------------------===//
-// Calling Conventions
+// CPU Directives
//
//===----------------------------------------------------------------------===//
-include "MipsCallingConv.td"
+def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true",
+ "MipsIII ISA Support">;
//===----------------------------------------------------------------------===//
// Mips processors supported.
//===----------------------------------------------------------------------===//
-class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, NoItineraries, Features>;
-
-def : Proc<"generic", []>;
-
-//===----------------------------------------------------------------------===//
-// Declare the target which we are implementing
-//===----------------------------------------------------------------------===//
+def : Processor<"generic", MipsGenericItineraries, []>;
+//def : Processor<"r4000", MipsR4000Itineraries, [FeatureMipsIII]>;
def Mips : Target {
- // Pull in Instruction Info:
let InstructionSet = MipsInstrInfo;
}
+
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=41159&r1=41158&r2=41159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Aug 17 21:18:07 2007
@@ -17,7 +17,8 @@
using namespace llvm;
MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
- const std::string &FS) : isR3000(false)
+ const std::string &FS) :
+ IsMipsIII(false)
{
std::string CPU = "generic";
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