Author: reid
Date: Tue Aug 7 12:12:43 2007
New Revision: 40900
URL: http://llvm.org/viewvc/llvm-project?rev=40900&view=rev
Log:
Add the code generation options.
Modified:
llvm/trunk/docs/CommandGuide/lli.pod
Modified: llvm/trunk/docs/CommandGuide/lli.pod
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/lli.pod?rev=40900&r1=40899&r2=40900&view=diff
==============================================================================
--- llvm/trunk/docs/CommandGuide/lli.pod (original)
+++ llvm/trunk/docs/CommandGuide/lli.pod Tue Aug 7 12:12:43 2007
@@ -115,6 +115,125 @@
=back
+=head1 CODE GENERATION OPTIONS
+
+=over
+
+=item B<-code-model>=I<model>
+
+Choose the code model from:
+
+=over
+
+=item I<default>: Target default code model
+
+=item I<small>: Small code model
+
+=item I<kernel>: Kernel code model
+=item I<medium>: Medium code model
+=item I<large>: Large code model
+
+=back
+
+=item B<-disable-post-RA-scheduler>
+
+Disable scheduling after register allocation.
+
+=item B<-disable-spill-fusing>
+
+Disable fusing of spill code into instructions.
+
+=item B<-enable-correct-eh-support>
+
+Make the -lowerinvoke pass insert expensive, but correct, EH code.
+
+=item B<-enable-eh>
+
+Exception handling should be emitted.
+
+=item B<-join-liveintervals>
+
+Coalesce copies (default=true).
+
+=item B<-nozero-initialized-in-bss>
+Don't place zero-initialized symbols into the BSS section.
+
+=item B<-pre-RA-sched>=I<scheduler>
+
+Instruction schedulers available (before register allocation):
+
+=over
+
+=item I<=default>: Best scheduler for the target
+
+=item I<=none>: No scheduling: breadth first sequencing
+
+=item I<=simple>: Simple two pass scheduling: minimize critical path and
maximize processor utilization
+
+=item I<=simple-noitin>: Simple two pass scheduling: Same as simple except
using generic latency
+
+=item I<=list-burr>: Bottom-up register reduction list scheduling
+
+=item I<=list-tdrr>: Top-down register reduction list scheduling
+
+=item I<=list-td>: Top-down list scheduler -print-machineinstrs - Print
generated machine code
+
+=back
+
+=item B<-regalloc>=I<allocator>
+
+Register allocator to use: (default = linearscan)
+
+=over
+
+=item I<=bigblock>: Big-block register allocator
+
+=item I<=linearscan>: linear scan register allocator =local - local register
allocator
+
+=item I<=simple>: simple register allocator
+
+=back
+
+=item B<-relocation-model>=I<model>
+
+Choose relocation model from:
+
+=over
+
+=item I<=default>: Target default relocation model
+
+=item I<=static>: Non-relocatable code =pic - Fully relocatable, position
independent code
+
+=item I<=dynamic-no-pic>: Relocatable external references, non-relocatable
code
+
+=back
+
+=item B<-spiller>
+
+Spiller to use: (default: local)
+
+=over
+
+=item I<=simple>: simple spiller
+
+=item I<=local>: local spiller
+
+=back
+
+=item B<-x86-asm-syntax>=I<syntax>
+
+Choose style of code to emit from X86 backend:
+
+=over
+
+=item I<=att>: Emit AT&T-style assembly
+
+=item I<=intel>: Emit Intel-style assembly
+
+=back
+
+=back
+
=head1 EXIT STATUS
If B<lli> fails to load the program, it will exit with an exit code of 1.
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