Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.10 -> 1.11
X86InstrInfo.cpp updated: 1.92 -> 1.93
X86InstrInfo.h updated: 1.67 -> 1.68
X86InstrInfo.td updated: 1.308 -> 1.309
X86InstrMMX.td updated: 1.33 -> 1.34
X86InstrSSE.td updated: 1.186 -> 1.187
---
Log message:
Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
---
Diffs of the changes: (+22 -23)
X86InstrFPStack.td | 2 ++
X86InstrInfo.cpp | 17 ++++-------------
X86InstrInfo.h | 2 +-
X86InstrInfo.td | 2 ++
X86InstrMMX.td | 14 ++++++++------
X86InstrSSE.td | 8 +++++---
6 files changed, 22 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.10
llvm/lib/Target/X86/X86InstrFPStack.td:1.11
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.10 Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/X86/X86InstrFPStack.td Mon Jun 25 19:48:07 2007
@@ -413,10 +413,12 @@
def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
// Floating point constant loads.
+let isReMaterializable = 1 in {
def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
[(set RFP:$dst, fp64imm0)]>;
def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
[(set RFP:$dst, fp64imm1)]>;
+}
def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.92
llvm/lib/Target/X86/X86InstrInfo.cpp:1.93
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.92 Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Mon Jun 25 19:48:07 2007
@@ -112,20 +112,9 @@
}
-bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
+bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
- case X86::FpLD0:
- case X86::FpLD1:
- case X86::MOV8ri:
- case X86::MOV16ri:
- case X86::MOV32ri:
- case X86::MMX_V_SET0:
- case X86::MMX_V_SETALLONES:
- case X86::V_SET0:
- case X86::V_SETALLONES:
- // These instructions are always trivially rematerializable.
- return true;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV16_rm:
@@ -146,7 +135,9 @@
MI->getOperand(2).getImmedValue() == 1 &&
MI->getOperand(3).getReg() == 0;
}
- return false;
+ // All other instructions marked M_REMATERIALIZABLE are always trivially
+ // rematerializable.
+ return true;
}
/// convertToThreeAddress - This method must be implemented by targets that
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.67
llvm/lib/Target/X86/X86InstrInfo.h:1.68
--- llvm/lib/Target/X86/X86InstrInfo.h:1.67 Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/X86/X86InstrInfo.h Mon Jun 25 19:48:07 2007
@@ -239,7 +239,7 @@
unsigned& destReg) const;
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- bool isTriviallyReMaterializable(MachineInstr *MI) const;
+ bool isReallyTriviallyReMaterializable(MachineInstr *MI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.308
llvm/lib/Target/X86/X86InstrInfo.td:1.309
--- llvm/lib/Target/X86/X86InstrInfo.td:1.308 Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Jun 25 19:48:07 2007
@@ -617,6 +617,7 @@
"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
"mov{l} {$src, $dst|$dst, $src}", []>;
+let isReMaterializable = 1 in {
def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(set GR8:$dst, imm:$src)]>;
@@ -626,6 +627,7 @@
def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
"mov{l} {$src, $dst|$dst, $src}",
[(set GR32:$dst, imm:$src)]>;
+}
def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(store (i8 imm:$src), addr:$dst)]>;
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.33
llvm/lib/Target/X86/X86InstrMMX.td:1.34
--- llvm/lib/Target/X86/X86InstrMMX.td:1.33 Mon Jun 18 20:48:05 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Jun 25 19:48:07 2007
@@ -503,12 +503,14 @@
// Alias instructions that map zero vector to pxor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
- "pxor $dst, $dst",
- [(set VR64:$dst, (v1i64 immAllZerosV))]>;
-def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
- "pcmpeqd $dst, $dst",
- [(set VR64:$dst, (v1i64 immAllOnesV))]>;
+let isReMaterializable = 1 in {
+ def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
+ "pxor $dst, $dst",
+ [(set VR64:$dst, (v1i64 immAllZerosV))]>;
+ def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
+ "pcmpeqd $dst, $dst",
+ [(set VR64:$dst, (v1i64 immAllOnesV))]>;
+}
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.186
llvm/lib/Target/X86/X86InstrSSE.td:1.187
--- llvm/lib/Target/X86/X86InstrSSE.td:1.186 Mon Jun 25 10:44:19 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 25 19:48:07 2007
@@ -762,6 +762,7 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
+let isReMaterializable = 1 in
def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
"xorps $dst, $dst",
[(set VR128:$dst, (v4f32 immAllZerosV))]>;
@@ -1821,9 +1822,10 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
- "pcmpeqd $dst, $dst",
- [(set VR128:$dst, (v2f64 immAllOnesV))]>;
+let isReMaterializable = 1 in
+ def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
+ "pcmpeqd $dst, $dst",
+ [(set VR128:$dst, (v2f64 immAllOnesV))]>;
// FR64 to 128-bit vector conversion.
def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
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