Changes in directory llvm/test/CodeGen/ARM:
ifcvt1.ll added (r1.1)
ifcvt2.ll added (r1.1)
ifcvt3.ll added (r1.1)
ifcvt4.ll added (r1.1)
ifcvt5.ll added (r1.1)
ifcvt6.ll added (r1.1)
ifcvt7.ll added (r1.1)
ifcvt8.ll added (r1.1)
---
Log message:
Added some if-conversion tests.
---
Diffs of the changes: (+201 -0)
ifcvt1.ll | 15 +++++++++++++++
ifcvt2.ll | 36 ++++++++++++++++++++++++++++++++++++
ifcvt3.ll | 19 +++++++++++++++++++
ifcvt4.ll | 38 ++++++++++++++++++++++++++++++++++++++
ifcvt5.ll | 24 ++++++++++++++++++++++++
ifcvt6.ll | 18 ++++++++++++++++++
ifcvt7.ll | 32 ++++++++++++++++++++++++++++++++
ifcvt8.ll | 19 +++++++++++++++++++
8 files changed, 201 insertions(+)
Index: llvm/test/CodeGen/ARM/ifcvt1.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt1.ll:1.1
*** /dev/null Wed Jun 20 13:26:25 2007
--- llvm/test/CodeGen/ARM/ifcvt1.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,15 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bx | wc
-l | grep 1
+
+ define i32 @t1(i32 %a, i32 %b) {
+ %tmp2 = icmp eq i32 %a, 0
+ br i1 %tmp2, label %cond_false, label %cond_true
+
+ cond_true:
+ %tmp5 = add i32 %b, 1
+ ret i32 %tmp5
+
+ cond_false:
+ %tmp7 = add i32 %b, -1
+ ret i32 %tmp7
+ }
Index: llvm/test/CodeGen/ARM/ifcvt2.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt2.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt2.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,36 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxlt |
wc -l | grep 2
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxgt |
wc -l | grep 1
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxge |
wc -l | grep 1
+
+ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+ %tmp2 = icmp sgt i32 %c, 10
+ %tmp5 = icmp slt i32 %d, 4
+ %tmp8 = or i1 %tmp5, %tmp2
+ %tmp13 = add i32 %b, %a
+ br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
+
+ cond_true:
+ %tmp15 = add i32 %tmp13, %c
+ %tmp1821 = sub i32 %tmp15, %d
+ ret i32 %tmp1821
+
+ UnifiedReturnBlock:
+ ret i32 %tmp13
+ }
+
+ define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
+ %tmp2 = icmp sgt i32 %c, 10
+ %tmp5 = icmp slt i32 %d, 4
+ %tmp8 = and i1 %tmp5, %tmp2
+ %tmp13 = add i32 %b, %a
+ br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
+
+ cond_true:
+ %tmp15 = add i32 %tmp13, %c
+ %tmp1821 = sub i32 %tmp15, %d
+ ret i32 %tmp1821
+
+ UnifiedReturnBlock:
+ ret i32 %tmp13
+ }
Index: llvm/test/CodeGen/ARM/ifcvt3.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt3.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt3.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,19 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep cmpne |
wc -l | grep 1
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bx | wc
-l | grep 2
+
+ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+ switch i32 %c, label %cond_next [
+ i32 1, label %cond_true
+ i32 7, label %cond_true
+ ]
+
+ cond_true:
+ %tmp12 = add i32 %a, 1
+ %tmp1518 = add i32 %tmp12, %b
+ ret i32 %tmp1518
+
+ cond_next:
+ %tmp15 = add i32 %b, %a
+ ret i32 %tmp15
+ }
Index: llvm/test/CodeGen/ARM/ifcvt4.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt4.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt4.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,38 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep subgt |
wc -l | grep 1
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep suble |
wc -l | grep 1
+ ; FIXME: Check for # of unconditional branch after adding branch folding post
ifcvt.
+
+ define i32 @t(i32 %a, i32 %b) {
+ entry:
+ %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp1434, label %bb17, label %bb.outer
+
+ bb.outer: ; preds = %cond_false, %entry
+ %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ]
; <i32> [#uses=5]
+ %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false
] ; <i32> [#uses=1]
+ br label %bb
+
+ bb: ; preds = %cond_true, %bb.outer
+ %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ]
; <i32> [#uses=2]
+ %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
+ %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
+ %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32>
[#uses=6]
+ %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1>
[#uses=1]
+ br i1 %tmp3, label %cond_true, label %cond_false
+
+ cond_true: ; preds = %bb
+ %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32>
[#uses=2]
+ %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp1437, label %bb17, label %bb
+
+ cond_false: ; preds = %bb
+ %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32>
[#uses=2]
+ %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1]
+ br i1 %tmp14, label %bb17, label %bb.outer
+
+ bb17: ; preds = %cond_false, %cond_true, %entry
+ %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [
%a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ ret i32 %a_addr.026.1
+ }
Index: llvm/test/CodeGen/ARM/ifcvt5.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt5.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt5.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,24 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep blge |
wc -l | grep 1
+
+ @x = external global i32* ; <i32**> [#uses=1]
+
+ define void @foo(i32 %a) {
+ entry:
+ %tmp = load i32** @x ; <i32*> [#uses=1]
+ store i32 %a, i32* %tmp
+ ret void
+ }
+
+ define void @t1(i32 %a, i32 %b) {
+ entry:
+ %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
+ br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
+
+ cond_true: ; preds = %entry
+ tail call void @foo( i32 %b )
+ ret void
+
+ UnifiedReturnBlock: ; preds = %entry
+ ret void
+ }
Index: llvm/test/CodeGen/ARM/ifcvt6.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt6.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt6.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,18 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep cmpne |
wc -l | grep 1
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep ldmhi |
wc -l | grep 1
+
+ define void @foo(i32 %X, i32 %Y) {
+ entry:
+ %tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1]
+ %tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
+ %tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1]
+ br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
+
+ cond_true: ; preds = %entry
+ %tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+ UnifiedReturnBlock: ; preds = %entry
+ ret void
+ }
Index: llvm/test/CodeGen/ARM/ifcvt7.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt7.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt7.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,32 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep cmpeq |
wc -l | grep 1
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep moveq |
wc -l | grep 1
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep ldmeq |
wc -l | grep 1
+ ; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of
BB1.
+
+ %struct.quad_struct = type { i32, i32, %struct.quad_struct*,
%struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*,
%struct.quad_struct* }
+
+ define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
+ entry:
+ br label %tailrecurse
+
+ tailrecurse: ; preds = %bb, %entry
+ %tmp6 = load %struct.quad_struct** null ;
<%struct.quad_struct*> [#uses=1]
+ %tmp9 = load %struct.quad_struct** null ;
<%struct.quad_struct*> [#uses=2]
+ %tmp12 = load %struct.quad_struct** null ;
<%struct.quad_struct*> [#uses=1]
+ %tmp14 = icmp eq %struct.quad_struct* null, null ; <i1>
[#uses=1]
+ %tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1>
[#uses=1]
+ %tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1>
[#uses=1]
+ %tmp29 = icmp eq %struct.quad_struct* %tmp12, null ; <i1>
[#uses=1]
+ %bothcond = and i1 %tmp17, %tmp14 ; <i1> [#uses=1]
+ %bothcond1 = and i1 %bothcond, %tmp23 ; <i1> [#uses=1]
+ %bothcond2 = and i1 %bothcond1, %tmp29 ; <i1> [#uses=1]
+ br i1 %bothcond2, label %return, label %bb
+
+ bb: ; preds = %tailrecurse
+ %tmp41 = tail call fastcc i32 @CountTree( %struct.quad_struct* %tmp9 )
; <i32> [#uses=0]
+ br label %tailrecurse
+
+ return: ; preds = %tailrecurse
+ ret i32 0
+ }
Index: llvm/test/CodeGen/ARM/ifcvt8.ll
diff -c /dev/null llvm/test/CodeGen/ARM/ifcvt8.ll:1.1
*** /dev/null Wed Jun 20 13:26:37 2007
--- llvm/test/CodeGen/ARM/ifcvt8.ll Wed Jun 20 13:26:15 2007
***************
*** 0 ****
--- 1,19 ----
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion
+ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep ldmne |
wc -l | grep 1
+
+ %struct.SString = type { i8*, i32, i32 }
+
+ declare void @abort()
+
+ define fastcc void @t(%struct.SString* %word, i8 sext %c) {
+ entry:
+ %tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1]
+ br i1 %tmp1, label %cond_true, label %cond_false
+
+ cond_true: ; preds = %entry
+ tail call void @abort( )
+ unreachable
+
+ cond_false: ; preds = %entry
+ ret void
+ }
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