Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.110 -> 1.111
---
Log message:
Add support to tablegen for specifying subregister classes on a per register
class basis.
---
Diffs of the changes: (+44 -0)
MRegisterInfo.h | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 44 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.110
llvm/include/llvm/Target/MRegisterInfo.h:1.111
--- llvm/include/llvm/Target/MRegisterInfo.h:1.110 Tue May 1 03:58:27 2007
+++ llvm/include/llvm/Target/MRegisterInfo.h Wed Jun 13 17:20:15 2007
@@ -64,6 +64,7 @@
const vt_iterator VTs;
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
+ const sc_iterator SubRegClasses;
const unsigned RegSize, Alignment; // Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
@@ -71,8 +72,10 @@
const MVT::ValueType *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
+ const TargetRegisterClass * const *subregcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+ SubRegClasses(subregcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@@ -167,6 +170,47 @@
return I;
}
+ /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
+ /// class of a sub-register class for this TargetRegisterClass.
+ bool hasSubRegForClass(const TargetRegisterClass *cs) const {
+ for (int i = 0; SubRegClasses[i] != NULL; ++i)
+ if (SubRegClasses[i] == cs)
+ return true;
+ return false;
+ }
+
+ /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
+ /// class of a sub-register class for this TargetRegisterClass.
+ bool hasClassForSubReg(unsigned SubReg) const {
+ --SubReg;
+ for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
+ if (i == SubReg)
+ return true;
+ return false;
+ }
+
+ /// getClassForSubReg - return theTargetRegisterClass for the sub-register
+ /// at idx for this TargetRegisterClass.
+ sc_iterator getClassForSubReg(unsigned SubReg) const {
+ --SubReg;
+ for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
+ if (i == SubReg)
+ return &SubRegClasses[i];
+ return NULL;
+ }
+
+ /// subregclasses_begin / subregclasses_end - Loop over all of
+ /// the subregister classes of this register class.
+ sc_iterator subregclasses_begin() const {
+ return SubRegClasses;
+ }
+
+ sc_iterator subregclasses_end() const {
+ sc_iterator I = SubRegClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
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