Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.217 -> 1.218
X86RegisterInfo.td updated: 1.42 -> 1.43
---
Log message:
Emit correct DWARF reg # for RA (return address) register
---
Diffs of the changes: (+7 -1)
X86RegisterInfo.cpp | 5 ++++-
X86RegisterInfo.td | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.217
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.218
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.217 Tue May 1 04:13:03 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed May 2 03:46:03 2007
@@ -1235,7 +1235,10 @@
}
unsigned X86RegisterInfo::getRARegister() const {
- return X86::ST0; // use a non-register register
+ if (Is64Bit)
+ return X86::RIP; // Should have dwarf #16
+ else
+ return X86::EIP; // Should have dwarf #8
}
unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.42
llvm/lib/Target/X86/X86RegisterInfo.td:1.43
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.42 Fri Apr 20 16:15:21 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.td Wed May 2 03:46:03 2007
@@ -60,6 +60,7 @@
def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>;
def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>;
def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>;
+ def IP : Register<"IP">, DwarfRegNum<8>;
// X86-64 only
def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
@@ -80,6 +81,7 @@
def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>;
def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>;
def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>;
+ def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<8>;
// X86-64 only
def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
@@ -109,6 +111,7 @@
def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
+ def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>;
// MMX Registers. These are actually aliased to ST0 .. ST7
def MM0 : Register<"MM0">, DwarfRegNum<29>;
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