Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.436 -> 1.437
---
Log message:
eliminate more redundant constraint type analysis
---
Diffs of the changes: (+2 -6)
SelectionDAGISel.cpp | 8 ++------
1 files changed, 2 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.436
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.437
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.436 Sat Apr 28
16:01:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 16:03:16 2007
@@ -3320,12 +3320,8 @@
switch (OpInfo.Type) {
case InlineAsm::isOutput: {
- TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
- if (OpInfo.ConstraintCode.size() == 1) // not a physreg name.
- CTy = TLI.getConstraintType(OpInfo.ConstraintCode);
-
- if (CTy != TargetLowering::C_RegisterClass &&
- CTy != TargetLowering::C_Register) {
+ if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
+ OpInfo.ConstraintType != TargetLowering::C_Register) {
// Memory output, or 'other' output (e.g. 'X' constraint).
SDOperand InOperandVal = OpInfo.CallOperand;
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