On Apr 2, 2007, at 1:11 PM, Chris Lattner wrote:
> On Mar 30, 2007, at 12:02 PM, Scott Michel wrote:
>> Spotted what was probably a long-standing bug, since some of my
>> cleanups
>> were simple substitutions.
>
> Sorry for the delay. In general, if you keep the changes as simple
> and disjoint as possible, I'm more likely to look at them soon :).
> Here you could split up the "allow custom legalize of rotates" part
> from the "introduce some temporary vars" part from "match ext
> rotate cases" part.
I did, I did, I did! Really! They're part and parcel of the same
functionality... :-)
>> +
>> + // Look for sign/zext/any-extended cases:
>> + if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
>> + || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
>> + || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
>> + (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
>> + || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
>> + || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
>> + SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
>> + SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
>> + if (RExtOp0.getOpcode() == ISD::SUB &&
>> + RExtOp0.getOperand(1) == LExtOp0) {
>> + // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
>> + // (rotr x, y)
>> + // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
>> + // (rotl x, (sub 32, y))
>> + if (ConstantSDNode *SUBC = cast<ConstantSDNode>
>> (RExtOp0.getOperand(0))) {
>> + if (SUBC->getValue() == OpSizeInBits) {
>> + if (HasROTL)
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> + else
>> + return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> + }
>
> Okay, but needs an extra level of spacing for the indentation here
> (2 spaces, not 1).
>
>> + }
>> + } else if (LExtOp0.getOpcode() == ISD::SUB &&
>> + RExtOp0 == LExtOp0.getOperand(1)) {
>> + // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
>> + // (rotl x, y)
>> + // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
>> + // (rotr x, (sub 32, y))
>> + if (ConstantSDNode *SUBC = cast<ConstantSDNode>
>> (LExtOp0.getOperand(0))) {
>> + if (SUBC->getValue() == OpSizeInBits) {
>> + if (HasROTL)
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> RHSShiftAmt).Val;
>> + else
>> + return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
>> LHSShiftAmt).Val;
>> + }
>
> Likewise.
Fixed tab violations, which made it look like incorrect indentation...
-scooter
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
