[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMInstrInfo.td ARMInstrThumb.td

[Lauro Ramos Venancio]

Changes in directory llvm/lib/Target/ARM:

ARMISelLowering.cpp updated: 1.30 -> 1.31
ARMInstrInfo.td updated: 1.93 -> 1.94
ARMInstrThumb.td updated: 1.18 -> 1.19
---
Log message:

bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of 
a CALL_NOLINK.


---
Diffs of the changes:  (+11 -11)

 ARMISelLowering.cpp |    6 +++---
 ARMInstrInfo.td     |    8 +++++---
 ARMInstrThumb.td    |    8 +++-----
 3 files changed, 11 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.30 
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.31
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.30        Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp     Tue Mar 27 11:19:21 2007
@@ -555,10 +555,10 @@
     CallOpc = (isDirect || Subtarget->hasV5TOps())
       ? ARMISD::CALL : ARMISD::CALL_NOLINK;
   }
-  if (CallOpc == ARMISD::CALL_NOLINK) {
-    // On CALL_NOLINK we must move PC to LR
+  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
+    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
     Chain = DAG.getCopyToReg(Chain, ARM::LR,
-                             DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
     InFlag = Chain.getValue(1);
   }
 


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.93 
llvm/lib/Target/ARM/ARMInstrInfo.td:1.94
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.93    Tue Mar 20 12:57:23 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Tue Mar 27 11:19:21 2007
@@ -370,6 +370,8 @@
   : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AI4<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AIx2<dag ops, string asm, list<dag> pattern>
+  : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
 class AI1x2<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
 
@@ -546,9 +548,9 @@
                [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
   let Uses = [LR] in {
     // ARMv4T
-    def BX : AI<(ops GPR:$dst, variable_ops),
-                "bx $dst",
-                [(ARMcall_nolink GPR:$dst)]>;
+    def BX : AIx2<(ops GPR:$dst, variable_ops),
+                  "mov lr, pc\n\tbx $dst",
+                  [(ARMcall_nolink GPR:$dst)]>;
   }
 }
 


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.18 
llvm/lib/Target/ARM/ARMInstrThumb.td:1.19
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.18   Tue Mar 20 12:57:23 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td        Tue Mar 27 11:19:21 2007
@@ -189,12 +189,10 @@
   def tBLXr : TI<(ops GPR:$dst, variable_ops),
                   "blx $dst",
                   [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
-  let Uses = [LR] in {
-    // ARMv4T
-    def tBX : TI<(ops GPR:$dst, variable_ops),
-                  "bx $dst",
+  // ARMv4T
+  def tBX : TIx2<(ops GPR:$dst, variable_ops),
+                  "cpy lr, pc\n\tbx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
-  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {



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