[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMISelLowering.cpp updated: 1.11 -> 1.12
---
Log message:

Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the 
RHS is a constant.

---
Diffs of the changes:  (+18 -20)

 ARMISelLowering.cpp |   38 ++++++++++++++++++--------------------
 1 files changed, 18 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.11 
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.12
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.11        Thu Feb  1 17:34:03 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp     Thu Feb  1 19:53:26 2007
@@ -859,7 +859,7 @@
   return false;
 }
 
-static bool isLegalCmpImmediate(int C, bool isThumb) {
+static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
   return ( isThumb && (C & ~255U) == 0) ||
          (!isThumb && ARM_AM::getSOImmVal(C) != -1);
 }
@@ -869,38 +869,36 @@
 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
                            SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
-    int C = (int)RHSC->getValue();
+    unsigned C = RHSC->getValue();
     if (!isLegalCmpImmediate(C, isThumb)) {
       // Constant does not fit, try adjusting it by one?
       switch (CC) {
       default: break;
       case ISD::SETLT:
-      case ISD::SETULT:
       case ISD::SETGE:
-      case ISD::SETUGE:
         if (isLegalCmpImmediate(C-1, isThumb)) {
-          switch (CC) {
-          default: break;
-          case ISD::SETLT:  CC = ISD::SETLE;  break;
-          case ISD::SETULT: CC = ISD::SETULE; break;
-          case ISD::SETGE:  CC = ISD::SETGT;  break;
-          case ISD::SETUGE: CC = ISD::SETUGT; break;
-          }
+          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
+          RHS = DAG.getConstant(C-1, MVT::i32);
+        }
+        break;
+      case ISD::SETULT:
+      case ISD::SETUGE:
+        if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
+          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
           RHS = DAG.getConstant(C-1, MVT::i32);
         }
         break;
       case ISD::SETLE:
-      case ISD::SETULE:
       case ISD::SETGT:
-      case ISD::SETUGT:
         if (isLegalCmpImmediate(C+1, isThumb)) {
-          switch (CC) {
-          default: break;
-          case ISD::SETLE:  CC = ISD::SETLT;  break;
-          case ISD::SETULE: CC = ISD::SETULT; break;
-          case ISD::SETGT:  CC = ISD::SETGE;  break;
-          case ISD::SETUGT: CC = ISD::SETUGE; break;
-          }
+          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
+          RHS = DAG.getConstant(C+1, MVT::i32);
+        }
+        break;
+      case ISD::SETULE:
+      case ISD::SETUGT:
+        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
+          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
           RHS = DAG.getConstant(C+1, MVT::i32);
         }
         break;



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