Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.463 -> 1.464
ScheduleDAGRRList.cpp updated: 1.25 -> 1.26
ScheduleDAGSimple.cpp updated: 1.23 -> 1.24
SelectionDAG.cpp updated: 1.379 -> 1.380
SelectionDAGISel.cpp updated: 1.353 -> 1.354
TargetLowering.cpp updated: 1.87 -> 1.88
---
Log message:
Fit in 80 columns
---
Diffs of the changes: (+19 -15)
LegalizeDAG.cpp | 8 ++++----
ScheduleDAGRRList.cpp | 12 +++++++-----
ScheduleDAGSimple.cpp | 4 ++--
SelectionDAG.cpp | 6 ++++--
SelectionDAGISel.cpp | 2 +-
TargetLowering.cpp | 2 +-
6 files changed, 19 insertions(+), 15 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.463
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.464
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.463 Wed Jan 31 03:29:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 31 22:55:59 2007
@@ -1516,7 +1516,7 @@
Tmp2 = LegalizeOp(Load.getValue(1));
break;
}
- assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be
supported!");
+ assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be
supported!");
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
@@ -1649,7 +1649,7 @@
// type should be returned by reference!
SDOperand Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi);
- Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,
Tmp3);
+ Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3,
Hi,Tmp3);
Result = LegalizeOp(Result);
}
}
@@ -4689,7 +4689,7 @@
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD) {
- Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
LD->getSrcValueOffset());
+ Lo = DAG.getLoad(NVT, Ch, Ptr,
LD->getSrcValue(),LD->getSrcValueOffset());
if (VT == MVT::f32 || VT == MVT::f64) {
// f32->i32 or f64->i64 one to one expansion.
// Remember that we legalized the chain.
@@ -4705,7 +4705,7 @@
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
getIntPtrConstant(IncrementSize));
// FIXME: This creates a bogus srcvalue!
- Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
LD->getSrcValueOffset());
+ Hi = DAG.getLoad(NVT, Ch, Ptr,
LD->getSrcValue(),LD->getSrcValueOffset());
// Build a factor node to remember that this load is independent of the
// other one.
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.25
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.26
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.25 Mon Jan 8
17:55:53 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Jan 31 22:55:59 2007
@@ -696,7 +696,8 @@
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
/// Smaller number is the higher priority.
template<class SF>
-unsigned BURegReductionPriorityQueue<SF>::CalcNodeSethiUllmanNumber(const
SUnit *SU) {
+unsigned BURegReductionPriorityQueue<SF>::
+CalcNodeSethiUllmanNumber(const SUnit *SU) {
unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
if (SethiUllmanNumber != 0)
return SethiUllmanNumber;
@@ -805,7 +806,8 @@
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
/// Smaller number is the higher priority.
template<class SF>
-unsigned TDRegReductionPriorityQueue<SF>::CalcNodeSethiUllmanNumber(const
SUnit *SU) {
+unsigned TDRegReductionPriorityQueue<SF>::
+CalcNodeSethiUllmanNumber(const SUnit *SU) {
unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
if (SethiUllmanNumber != 0)
return SethiUllmanNumber;
@@ -816,8 +818,8 @@
else if (SU->NumSuccsLeft == 0)
// If SU does not have a use, i.e. it doesn't produce a value that would
// be consumed (e.g. store), then it terminates a chain of computation.
- // Give it a small SethiUllman number so it will be scheduled right before
its
- // predecessors that it doesn't lengthen their live ranges.
+ // Give it a small SethiUllman number so it will be scheduled right before
+ // its predecessors that it doesn't lengthen their live ranges.
SethiUllmanNumber = 0;
else if (SU->NumPredsLeft == 0 &&
(Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
@@ -868,6 +870,6 @@
SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
- new
TDRegReductionPriorityQueue<td_ls_rr_sort>());
+ new
TDRegReductionPriorityQueue<td_ls_rr_sort>());
}
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.23
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.24
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.23 Sun Dec 17
05:15:53 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp Wed Jan 31 22:55:59 2007
@@ -277,7 +277,7 @@
/// ResourceTally - Manages the use of resources over time intervals. Each
/// item (slot) in the tally vector represents the resources used at a given
/// moment. A bit set to 1 indicates that a resource is in use, otherwise
-/// available. An assumption is made that the tally is large enough to
schedule
+/// available. An assumption is made that the tally is large enough to
schedule
/// all current instructions (asserts otherwise.)
///
template<class T>
@@ -377,7 +377,7 @@
// Try at cursor, if successful return position.
if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
// Locate a better position
- Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles,
StageBegin->Units);
+ Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
}
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.379
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.380
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.379 Mon Jan 29
16:58:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 31 22:55:59 2007
@@ -1577,7 +1577,8 @@
}
SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
- SDOperand Chain, SDOperand Ptr, const Value
*SV,
+ SDOperand Chain, SDOperand Ptr,
+ const Value *SV,
int SVOffset, MVT::ValueType EVT,
bool isVolatile) {
// If they are asking for an extending load from/to the same thing, return a
@@ -2228,7 +2229,8 @@
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
- SDOperand Op1, SDOperand Op2, SDOperand
Op3) {
+ SDOperand Op1, SDOperand Op2,
+ SDOperand Op3) {
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.353
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.354
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.353 Wed Jan 31
19:21:12 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jan 31 22:55:59 2007
@@ -3216,7 +3216,7 @@
// Figure out if there is a Packed type corresponding to this Vector
// type. If so, convert to the packed type.
- MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),
NumElems);
+ MVT::ValueType TVT =
MVT::getVectorType(getValueType(EltTy),NumElems);
if (TVT != MVT::Other && isTypeLegal(TVT)) {
// Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
// "N x PTyElementVT" MVT::Vector type.
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.87
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.88
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.87 Wed Jan 31
03:29:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jan 31 22:55:59 2007
@@ -715,7 +715,7 @@
// If none of the top bits are demanded, convert this into an any_extend.
if (NewBits == 0)
- return TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
+ return
TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
Op.getOperand(0)));
// Since some of the sign extended bits are demanded, we know that the sign
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