Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.44 -> 1.45
---
Log message:
Thumb eliminateFrameIndex fixes.
---
Diffs of the changes: (+27 -8)
ARMRegisterInfo.cpp | 35 +++++++++++++++++++++++++++--------
1 files changed, 27 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.44
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.45
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.44 Mon Jan 29 19:18:38 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Jan 29 20:36:01 2007
@@ -336,22 +336,27 @@
bool isMul4 = (Bytes & 3) == 0;
bool isTwoAddr = false;
unsigned NumBits = 1;
+ unsigned Scale = 1;
unsigned Opc = 0;
unsigned ExtraOpc = 0;
if (DestReg == BaseReg && BaseReg == ARM::SP) {
assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
- Bytes >>= 2; // Implicitly multiplied by 4.
NumBits = 7;
+ Scale = 4;
Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
isTwoAddr = true;
} else if (!isSub && BaseReg == ARM::SP) {
+ // r1 = add sp, 403
+ // =>
+ // r1 = add sp, 100 * 4
+ // r1 = add r1, 3
if (!isMul4) {
Bytes &= ~3;
ExtraOpc = ARM::tADDi3;
}
- Bytes >>= 2; // Implicitly multiplied by 4.
NumBits = 8;
+ Scale = 4;
Opc = ARM::tADDrSPi;
} else {
if (DestReg != BaseReg) {
@@ -372,10 +377,11 @@
isTwoAddr = true;
}
- unsigned Chunk = (1 << NumBits) - 1;
+ unsigned Chunk = ((1 << NumBits) - 1) * Scale;
while (Bytes) {
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
- Bytes -= ThisVal;
+ Bytes -= ThisVal;
+ ThisVal /= Scale;
// Build the new tADD / tSUB.
if (isTwoAddr)
BuildMI(MBB, MBBI, TII.get(Opc),
DestReg).addReg(DestReg).addImm(ThisVal);
@@ -388,6 +394,8 @@
// r4 = add r4, imm
// ...
NumBits = 8;
+ Scale = 1;
+ Chunk = ((1 << NumBits) - 1) * Scale;
Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
isTwoAddr = true;
}
@@ -636,6 +644,13 @@
}
// Otherwise, it didn't fit. Pull in what we can to simplify the
immediate.
+ if (AddrMode == ARMII::AddrModeTs) {
+ // Thumb tLDRspi, tSTRspi. These will change to instructions that use a
+ // different base register.
+ NumBits = 5;
+ Mask = (1 << NumBits) - 1;
+ }
+
ImmedOffset = ImmedOffset & Mask;
if (isSub)
ImmedOffset |= 1 << NumBits;
@@ -654,7 +669,9 @@
unsigned TmpReg = MI.getOperand(0).getReg();
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
isSub ? -Offset : Offset, TII);
+ MI.setInstrDescriptor(TII.get(ARM::tLDR));
MI.getOperand(i).ChangeToRegister(TmpReg, false);
+ MI.addRegOperand(0, false); // tLDR has an extra register operand.
} else if (TII.isStore(Opcode)) {
// FIXME! This is horrific!!! We need register scavenging.
// Our temporary workaround has marked r3 unavailable. Of course, r3 is
@@ -664,16 +681,18 @@
// Use r2 to materialize sp + offset
// str r12, r2
// r2 = r12
- unsigned DestReg = MI.getOperand(0).getReg();
+ unsigned ValReg = MI.getOperand(0).getReg();
unsigned TmpReg = ARM::R3;
- if (DestReg == ARM::R3) {
+ if (ValReg == ARM::R3) {
BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
TmpReg = ARM::R2;
}
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
isSub ? -Offset : Offset, TII);
- MI.getOperand(i).ChangeToRegister(DestReg, false);
- if (DestReg == ARM::R3)
+ MI.setInstrDescriptor(TII.get(ARM::tSTR));
+ MI.getOperand(i).ChangeToRegister(TmpReg, false);
+ MI.addRegOperand(0, false); // tSTR has an extra register operand.
+ if (ValReg == ARM::R3)
BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
} else
assert(false && "Unexpected opcode!");
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