Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.92 -> 1.93 ARMInstrInfo.td updated: 1.81 -> 1.82 --- Log message: Implement SELECT_CC (f32/f64) for ARM. --- Diffs of the changes: (+16 -2) ARMISelDAGToDAG.cpp | 4 +++- ARMInstrInfo.td | 14 +++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.92 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.93 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.92 Thu Dec 14 12:58:37 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Dec 28 07:11:14 2006 @@ -73,6 +73,8 @@ setOperationAction(ISD::SETCC, MVT::f64, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); setOperationAction(ISD::MEMSET, MVT::Other, Expand); @@ -745,7 +747,7 @@ SDOperand Cmp; SDOperand ARMCC; LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG); - return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp); + return DAG.getNode(ARMISD::SELECT, Op.getValueType(), TrueVal, FalseVal, ARMCC, Cmp); } static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.81 llvm/lib/Target/ARM/ARMInstrInfo.td:1.82 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.81 Thu Dec 28 06:51:40 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Thu Dec 28 07:11:14 2006 @@ -102,7 +102,7 @@ def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet, [SDNPHasChain, SDNPOptInFlag]>; -def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>; +def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>; def SDTarmfmstat : SDTypeProfile<0, 0, []>; @@ -209,6 +209,18 @@ "mov$cc $dst, $true", [(set IntRegs:$dst, (armselect addr_mode1:$true, IntRegs:$false, imm:$cc))]>; + + def fcpyscond : InstARM<(ops FPRegs:$dst, FPRegs:$false, + FPRegs:$true, CCOp:$cc), + "fcpys$cc $dst, $true", + [(set FPRegs:$dst, (armselect FPRegs:$true, + FPRegs:$false, imm:$cc))]>; + + def fcpydcond : InstARM<(ops DFPRegs:$dst, DFPRegs:$false, + DFPRegs:$true, CCOp:$cc), + "fcpyd$cc $dst, $true", + [(set DFPRegs:$dst, (armselect DFPRegs:$true, + DFPRegs:$false, imm:$cc))]>; } def MUL : IntBinOp<"mul", mul>; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits