Changes in directory llvm/lib/Target/PowerPC:
PPCCodeEmitter.cpp updated: 1.72 -> 1.73
PPCISelLowering.cpp updated: 1.243 -> 1.244
PPCSubtarget.cpp updated: 1.26 -> 1.27
PPCSubtarget.h updated: 1.18 -> 1.19
PPCTargetMachine.cpp updated: 1.109 -> 1.110
---
Log message:
Another step forward in PPC64 JIT support: we now no-longer need stubs
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
---
Diffs of the changes: (+83 -33)
PPCCodeEmitter.cpp | 52 +++++++++++++++++++++++++++------------------------
PPCISelLowering.cpp | 3 --
PPCSubtarget.cpp | 38 +++++++++++++++++++++++++++++++++----
PPCSubtarget.h | 18 +++++++++++++++--
PPCTargetMachine.cpp | 5 +++-
5 files changed, 83 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.72
llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.73
--- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.72 Thu Dec 7 22:54:03 2006
+++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Dec 11 17:22:44 2006
@@ -136,15 +136,9 @@
if (MI.getOpcode() == PPC::BL || MI.getOpcode() == PPC::BL8)
Reloc = PPC::reloc_pcrel_bx;
else {
- // If in PIC mode, we need to encode the negated address of the
- // 'movepctolr' into the unrelocated field. After relocation, we'll have
- // &gv-&movepctolr in the imm field. Once &movepctolr is added to the
imm
- // field, we get &gv.
if (TM.getRelocationModel() == Reloc::PIC_) {
assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
- rv = -(intptr_t)MovePCtoLROffset - 4;
}
-
switch (MI.getOpcode()) {
default: MI.dump(); assert(0 && "Unknown instruction for relocation!");
case PPC::LIS:
@@ -152,7 +146,6 @@
case PPC::ADDIS:
case PPC::ADDIS8:
Reloc = PPC::reloc_absolute_high; // Pointer to symbol
- rv >>= 16;
break;
case PPC::LI:
case PPC::LI8:
@@ -173,7 +166,6 @@
case PPC::STFS:
case PPC::STFD:
Reloc = PPC::reloc_absolute_low;
- rv &= 0xFFFF;
break;
case PPC::LWA:
@@ -181,25 +173,37 @@
case PPC::STD:
case PPC::STD_32:
Reloc = PPC::reloc_absolute_low_ix;
- rv &= 0xFFFF;
- rv >>= 2;
break;
}
}
- if (MO.isGlobalAddress())
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- Reloc, MO.getGlobal(), 0));
- else if (MO.isExternalSymbol())
- MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
- Reloc, MO.getSymbolName(), 0));
- else if (MO.isConstantPoolIndex())
- MCE.addRelocation(MachineRelocation::getConstPool(
- MCE.getCurrentPCOffset(),
- Reloc, MO.getConstantPoolIndex(),
0));
- else // isJumpTableIndex
- MCE.addRelocation(MachineRelocation::getJumpTable(
- MCE.getCurrentPCOffset(),
- Reloc, MO.getJumpTableIndex(), 0));
+
+ MachineRelocation R;
+ if (MO.isGlobalAddress()) {
+ R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ MO.getGlobal(), 0);
+ } else if (MO.isExternalSymbol()) {
+ R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
+ Reloc, MO.getSymbolName(), 0);
+ } else if (MO.isConstantPoolIndex()) {
+ R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
+ Reloc, MO.getConstantPoolIndex(), 0);
+ } else {
+ assert(MO.isJumpTableIndex());
+ R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
+ Reloc, MO.getJumpTableIndex(), 0);
+ }
+
+ // If in PIC mode, we need to encode the negated address of the
+ // 'movepctolr' into the unrelocated field. After relocation, we'll have
+ // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the
imm
+ // field, we get &gv. This doesn't happen for branch relocations, which
are
+ // always implicitly pc relative.
+ if (TM.getRelocationModel() == Reloc::PIC_ && Reloc !=
PPC::reloc_pcrel_bx){
+ assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
+ R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
+ }
+ MCE.addRelocation(R);
+
} else if (MO.isMachineBasicBlock()) {
unsigned Reloc = 0;
unsigned Opcode = MI.getOpcode();
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.243
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.244
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.243 Mon Dec 11 12:45:56 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Dec 11 17:22:45 2006
@@ -1015,8 +1015,7 @@
Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
- if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
- (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
+ if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
return Lo;
// If the global is weak or external, we have to go through the lazy
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.26
llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.27
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.26 Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp Mon Dec 11 17:22:45 2006
@@ -14,6 +14,7 @@
#include "PPCSubtarget.h"
#include "PPC.h"
#include "llvm/Module.h"
+#include "llvm/Target/TargetMachine.h"
#include "PPCGenSubtarget.inc"
using namespace llvm;
@@ -55,9 +56,10 @@
#endif
-PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool
is64Bit)
- : StackAlignment(16)
- , InstrItins()
+PPCSubtarget::PPCSubtarget(const TargetMachine &tm, const Module &M,
+ const std::string &FS, bool is64Bit)
+ : TM(tm)
+ , StackAlignment(16)
, IsGigaProcessor(false)
, Has64BitSupport(false)
, Use64BitRegs(false)
@@ -65,7 +67,8 @@
, HasAltivec(false)
, HasFSQRT(false)
, HasSTFIWX(false)
- , IsDarwin(false) {
+ , IsDarwin(false)
+ , HasLazyResolverStubs(false) {
// Determine default and user specified characteristics
std::string CPU = "generic";
@@ -105,4 +108,31 @@
IsDarwin = true;
#endif
}
+
+ // Set up darwin-specific properties.
+ if (IsDarwin) {
+ HasLazyResolverStubs = true;
+ }
+}
+
+/// SetJITMode - This is called to inform the subtarget info that we are
+/// producing code for the JIT.
+void PPCSubtarget::SetJITMode() {
+ // JIT mode doesn't want lazy resolver stubs, it knows exactly where
+ // everything is. This matters for PPC64, which codegens in PIC mode without
+ // stubs.
+ HasLazyResolverStubs = false;
+}
+
+
+/// hasLazyResolverStub - Return true if accesses to the specified global have
+/// to go through a dyld lazy resolution stub. This means that an extra load
+/// is required to get the address of the global.
+bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
+ // We never hae stubs if HasLazyResolverStubs=false or if in static mode.
+ if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
+ return false;
+
+ return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
+ (GV->isExternal() && !GV->hasNotBeenReadFromBytecode());
}
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.h:1.18
llvm/lib/Target/PowerPC/PPCSubtarget.h:1.19
--- llvm/lib/Target/PowerPC/PPCSubtarget.h:1.18 Mon Dec 11 15:42:55 2006
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h Mon Dec 11 17:22:45 2006
@@ -21,9 +21,13 @@
namespace llvm {
class Module;
-
+class GlobalValue;
+class TargetMachine;
+
class PPCSubtarget : public TargetSubtarget {
protected:
+ const TargetMachine &TM;
+
/// stackAlignment - The minimum alignment known to hold of the stack frame
on
/// entry to the function and which must be maintained by every function.
unsigned StackAlignment;
@@ -40,15 +44,21 @@
bool HasFSQRT;
bool HasSTFIWX;
bool IsDarwin;
+ bool HasLazyResolverStubs;
public:
/// This constructor initializes the data members to match that
/// of the specified module.
///
- PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit);
+ PPCSubtarget(const TargetMachine &TM, const Module &M,
+ const std::string &FS, bool is64Bit);
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+
+ /// SetJITMode - This is called to inform the subtarget info that we are
+ /// producing code for the JIT.
+ void SetJITMode();
/// getStackAlignment - Returns the minimum alignment known to hold of the
/// stack frame on entry to the function and which must be maintained by
every
@@ -78,6 +88,10 @@
/// has64BitSupport() returns true.
bool use64BitRegs() const { return Use64BitRegs; }
+ /// hasLazyResolverStub - Return true if accesses to the specified global
have
+ /// to go through a dyld lazy resolution stub. This means that an extra load
+ /// is required to get the address of the global.
+ bool hasLazyResolverStub(const GlobalValue *GV) const;
// Specific obvious features.
bool hasFSQRT() const { return HasFSQRT; }
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.109
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.110
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.109 Thu Dec 7 22:54:03 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Dec 11 17:22:45 2006
@@ -81,7 +81,7 @@
PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
bool is64Bit)
- : Subtarget(M, FS, is64Bit),
+ : Subtarget(*this, M, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
@@ -146,6 +146,9 @@
setRelocationModel(Reloc::Static);
}
+ // Inform the subtarget that we are in JIT mode. FIXME: does this break
macho
+ // writing?
+ Subtarget.SetJITMode();
// Machine code emitter pass for PowerPC.
PM.add(createPPCCodeEmitterPass(*this, MCE));
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