Changes in directory llvm/lib/CodeGen:
LLVMTargetMachine.cpp updated: 1.6 -> 1.7
LiveVariables.cpp updated: 1.63 -> 1.64
MachOWriter.cpp updated: 1.7 -> 1.8
MachineBasicBlock.cpp updated: 1.35 -> 1.36
MachineFunction.cpp updated: 1.104 -> 1.105
RegAllocSimple.cpp updated: 1.78 -> 1.79
TwoAddressInstructionPass.cpp updated: 1.43 -> 1.44
---
Log message:
Removed more <iostream> includes
---
Diffs of the changes: (+30 -38)
LLVMTargetMachine.cpp | 21 ++++++++++-----------
LiveVariables.cpp | 19 +++++++++----------
MachOWriter.cpp | 1 -
MachineBasicBlock.cpp | 3 +--
MachineFunction.cpp | 14 ++++++--------
RegAllocSimple.cpp | 3 +--
TwoAddressInstructionPass.cpp | 7 +++----
7 files changed, 30 insertions(+), 38 deletions(-)
Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp
diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.6
llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.7
--- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.6 Wed Nov 15 19:00:07 2006
+++ llvm/lib/CodeGen/LLVMTargetMachine.cpp Thu Dec 7 14:28:15 2006
@@ -17,7 +17,6 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Scalar.h"
-#include <iostream>
using namespace llvm;
bool LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
@@ -46,18 +45,18 @@
// Print the instruction selected machine code...
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Run post-ra passes.
if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Insert prolog/epilog code. Eliminate abstract frame index references...
@@ -71,11 +70,11 @@
PM.add(createDebugLabelFoldingPass());
if (PrintMachineCode) // Print the register-allocated code
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
switch (FileType) {
@@ -127,32 +126,32 @@
// Print the instruction selected machine code...
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Run post-ra passes.
if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter());
if (PrintMachineCode) // Print the register-allocated code
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (!Fast)
PM.add(createBranchFoldingPass());
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ PM.add(createMachineFunctionPrinterPass(cerr.stream()));
addCodeEmitter(PM, Fast, MCE);
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.63
llvm/lib/CodeGen/LiveVariables.cpp:1.64
--- llvm/lib/CodeGen/LiveVariables.cpp:1.63 Wed Nov 15 14:51:59 2006
+++ llvm/lib/CodeGen/LiveVariables.cpp Thu Dec 7 14:28:15 2006
@@ -35,27 +35,26 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/Config/alloca.h"
#include <algorithm>
-#include <iostream>
using namespace llvm;
static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
void LiveVariables::VarInfo::dump() const {
- std::cerr << "Register Defined by: ";
+ cerr << "Register Defined by: ";
if (DefInst)
- std::cerr << *DefInst;
+ cerr << *DefInst;
else
- std::cerr << "<null>\n";
- std::cerr << " Alive in blocks: ";
+ cerr << "<null>\n";
+ cerr << " Alive in blocks: ";
for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
- if (AliveBlocks[i]) std::cerr << i << ", ";
- std::cerr << "\n Killed by:";
+ if (AliveBlocks[i]) cerr << i << ", ";
+ cerr << "\n Killed by:";
if (Kills.empty())
- std::cerr << " No instructions.\n";
+ cerr << " No instructions.\n";
else {
for (unsigned i = 0, e = Kills.size(); i != e; ++i)
- std::cerr << "\n #" << i << ": " << *Kills[i];
- std::cerr << "\n";
+ cerr << "\n #" << i << ": " << *Kills[i];
+ cerr << "\n";
}
}
Index: llvm/lib/CodeGen/MachOWriter.cpp
diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.7
llvm/lib/CodeGen/MachOWriter.cpp:1.8
--- llvm/lib/CodeGen/MachOWriter.cpp:1.7 Thu Nov 16 14:04:04 2006
+++ llvm/lib/CodeGen/MachOWriter.cpp Thu Dec 7 14:28:15 2006
@@ -32,7 +32,6 @@
#include "llvm/Support/Mangler.h"
#include "llvm/Support/MathExtras.h"
#include <algorithm>
-#include <iostream>
using namespace llvm;
//===----------------------------------------------------------------------===//
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.35
llvm/lib/CodeGen/MachineBasicBlock.cpp:1.36
--- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.35 Mon Nov 27 17:36:08 2006
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp Thu Dec 7 14:28:15 2006
@@ -19,7 +19,6 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/LeakDetector.h"
-#include <iostream>
#include <algorithm>
using namespace llvm;
@@ -87,7 +86,7 @@
}
void MachineBasicBlock::dump() const {
- print(std::cerr);
+ print(*cerr.stream());
}
void MachineBasicBlock::print(std::ostream &OS) const {
Index: llvm/lib/CodeGen/MachineFunction.cpp
diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.104
llvm/lib/CodeGen/MachineFunction.cpp:1.105
--- llvm/lib/CodeGen/MachineFunction.cpp:1.104 Sat Oct 28 13:17:09 2006
+++ llvm/lib/CodeGen/MachineFunction.cpp Thu Dec 7 14:28:15 2006
@@ -31,9 +31,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/Config/config.h"
#include <fstream>
-#include <iostream>
#include <sstream>
-
using namespace llvm;
static AnnotationID MF_AID(
@@ -177,7 +175,7 @@
}
-void MachineFunction::dump() const { print(std::cerr); }
+void MachineFunction::dump() const { print(*cerr.stream()); }
void MachineFunction::print(std::ostream &OS) const {
OS << "# Machine code for " << Fn->getName () << "():\n";
@@ -268,8 +266,8 @@
#ifndef NDEBUG
ViewGraph(this, "mf" + getFunction()->getName());
#else
- std::cerr << "SelectionDAG::viewGraph is only available in debug builds on "
- << "systems with Graphviz or gv!\n";
+ cerr << "SelectionDAG::viewGraph is only available in debug builds on "
+ << "systems with Graphviz or gv!\n";
#endif // NDEBUG
}
@@ -350,7 +348,7 @@
}
void MachineFrameInfo::dump(const MachineFunction &MF) const {
- print(MF, std::cerr);
+ print(MF, *cerr.stream());
}
@@ -390,7 +388,7 @@
return TD->getPointerAlignment();
}
-void MachineJumpTableInfo::dump() const { print(std::cerr); }
+void MachineJumpTableInfo::dump() const { print(*cerr.stream()); }
//===----------------------------------------------------------------------===//
@@ -473,4 +471,4 @@
}
}
-void MachineConstantPool::dump() const { print(std::cerr); }
+void MachineConstantPool::dump() const { print(*cerr.stream()); }
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.78
llvm/lib/CodeGen/RegAllocSimple.cpp:1.79
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.78 Wed Dec 6 11:46:31 2006
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Thu Dec 7 14:28:15 2006
@@ -27,7 +27,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
using namespace llvm;
namespace {
@@ -192,7 +191,7 @@
unsigned virtualReg = (unsigned) op.getReg();
DOUT << "op: " << op << "\n";
DOUT << "\t inst[" << i << "]: ";
- DEBUG(MI->print(std::cerr, TM));
+ DEBUG(MI->print(*cerr.stream(), TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.43
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.44
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.43 Wed Dec 6 11:46:31 2006
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Dec 7 14:28:15 2006
@@ -41,7 +41,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
using namespace llvm;
namespace {
@@ -102,7 +101,7 @@
if (FirstTied) {
++NumTwoAddressInstrs;
- DOUT << '\t'; DEBUG(mi->print(std::cerr, &TM));
+ DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
}
FirstTied = false;
@@ -195,7 +194,7 @@
MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
MachineBasicBlock::iterator prevMi = prior(mi);
- DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(std::cerr, &TM));
+ DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
// Update live variables for regA
LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
@@ -220,7 +219,7 @@
mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
MadeChange = true;
- DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(std::cerr, &TM));
+ DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
}
}
}
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