Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.418 -> 1.419 --- Log message: Fix PR1016: http://llvm.org/PR1016 --- Diffs of the changes: (+4 -5) LegalizeDAG.cpp | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.418 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.419 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.418 Sun Nov 26 22:39:56 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 27 19:03:30 2006 @@ -1862,6 +1862,10 @@ break; case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. + // Make sure the condition is either zero or one. + if (!TLI.MaskedValueIsZero(Tmp1, + MVT::getIntVTBitMask(Tmp1.getValueType())^1)) + Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); break; } Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal @@ -1883,11 +1887,6 @@ Tmp2, Tmp3, cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); } else { - // Make sure the condition is either zero or one. It may have been - // promoted from something else. - unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType()); - if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1)) - Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); Result = DAG.getSelectCC(Tmp1, DAG.getConstant(0, Tmp1.getValueType()), Tmp2, Tmp3, ISD::SETNE); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
