[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.246 -> 1.247
---
Log message:

Don't attempt expensive pre-/post- indexed dag combine if target does not 
support them.

---
Diffs of the changes:  (+18 -1)

 DAGCombiner.cpp |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.246 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.247
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.246 Thu Nov  9 11:54:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp       Thu Nov  9 13:10:46 2006
@@ -190,9 +190,18 @@
 
       bool isLoad = true;
       SDOperand Ptr;
+      MVT::ValueType VT;
       if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
+        VT = LD->getLoadedVT();
+        if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
+            !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
+          return false;
         Ptr = LD->getBasePtr();
       } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
+        VT = ST->getStoredVT();
+        if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
+            !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
+          return false;
         Ptr = ST->getBasePtr();
         isLoad = false;
       } else
@@ -281,8 +290,16 @@
       SDOperand Ptr;
       MVT::ValueType VT;
       if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
+        VT = LD->getLoadedVT();
+        if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
+            !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
+          return false;
         Ptr = LD->getBasePtr();
       } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
+        VT = ST->getStoredVT();
+        if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
+            !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
+          return false;
         Ptr = ST->getBasePtr();
         isLoad = false;
       } else
@@ -299,7 +316,7 @@
           SDOperand BasePtr;
           SDOperand Offset;
           ISD::MemIndexedMode AM = ISD::UNINDEXED;
-          if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
+          if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) 
{
             if (Ptr == Offset)
               std::swap(BasePtr, Offset);
             if (Ptr != BasePtr)



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