Changes in directory llvm/lib/Target/X86:
X86CodeEmitter.cpp updated: 1.120 -> 1.121
X86RegisterInfo.cpp updated: 1.172 -> 1.173
---
Log message:
Remove M_2_ADDR_FLAG.
---
Diffs of the changes: (+9 -5)
X86CodeEmitter.cpp | 7 +++++--
X86RegisterInfo.cpp | 7 ++++---
2 files changed, 9 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.120
llvm/lib/Target/X86/X86CodeEmitter.cpp:1.121
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.120 Wed Sep 13 14:07:28 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed Nov 8 20:22:54 2006
@@ -470,7 +470,8 @@
REX |= 1 << 3;
if (MI.getNumOperands()) {
- bool isTwoAddr = (Desc.Flags & M_2_ADDR_FLAG) != 0;
+ bool isTwoAddr = II->getNumOperands(Opcode) > 1 &&
+ II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX
prefix.
bool isTrunc8 = isX86_64TruncToByte(Opcode);
@@ -607,7 +608,9 @@
// If this is a two-address instruction, skip one of the register operands.
unsigned CurOp = 0;
- CurOp += (Desc.Flags & M_2_ADDR_FLAG) != 0;
+ if (II->getNumOperands(Opcode) > 1 &&
+ II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1)
+ CurOp++;
unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.172
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.173
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.172 Thu Nov 2 20:08:41 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Nov 8 20:22:54 2006
@@ -284,14 +284,15 @@
const TableEntry *OpcodeTablePtr = NULL;
unsigned OpcodeTableSize = 0;
bool isTwoAddrFold = false;
+ bool isTwoAddr = TII.getNumOperands(MI->getOpcode()) > 1 &&
+ TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) !=
-1;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
- if (MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() &&
+ if (isTwoAddr && MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg() && i < 2 &&
- MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
- TII.isTwoAddrInstr(MI->getOpcode())) {
+ MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
static const TableEntry OpcodeTable[] = {
{ X86::ADC32ri, X86::ADC32mi },
{ X86::ADC32ri8, X86::ADC32mi8 },
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