Changes in directory llvm/docs:
LangRef.html updated: 1.162 -> 1.163 --- Log message: For PR950: http://llvm.org/PR950 : This patch converts the old SHR instruction into two instructions, AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not dependent on the sign of their operands. --- Diffs of the changes: (+54 -19) LangRef.html | 73 +++++++++++++++++++++++++++++++++++++++++++---------------- 1 files changed, 54 insertions(+), 19 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.162 llvm/docs/LangRef.html:1.163 --- llvm/docs/LangRef.html:1.162 Tue Nov 7 19:18:52 2006 +++ llvm/docs/LangRef.html Wed Nov 8 00:47:32 2006 @@ -92,7 +92,8 @@ <li><a href="#i_or">'<tt>or</tt>' Instruction</a></li> <li><a href="#i_xor">'<tt>xor</tt>' Instruction</a></li> <li><a href="#i_shl">'<tt>shl</tt>' Instruction</a></li> - <li><a href="#i_shr">'<tt>shr</tt>' Instruction</a></li> + <li><a href="#i_lshr">'<tt>lshr</tt>' Instruction</a></li> + <li><a href="#i_ashr">'<tt>ashr</tt>' Instruction</a></li> </ol> </li> <li><a href="#vectorops">Vector Operations</a> @@ -2070,30 +2071,64 @@ </pre> </div> <!-- _______________________________________________________________________ --> -<div class="doc_subsubsection"> <a name="i_shr">'<tt>shr</tt>' +<div class="doc_subsubsection"> <a name="i_lshr">'<tt>lshr</tt>' Instruction</a> </div> <div class="doc_text"> <h5>Syntax:</h5> -<pre> <result> = shr <ty> <var1>, ubyte <var2> <i>; yields {ty}:result</i> +<pre> <result> = lshr <ty> <var1>, ubyte <var2> <i>; yields {ty}:result</i> </pre> + <h5>Overview:</h5> -<p>The '<tt>shr</tt>' instruction returns the first operand shifted to -the right a specified number of bits.</p> +<p>The '<tt>lshr</tt>' instruction (logical shift right) returns the first +operand shifted to the right a specified number of bits.</p> + <h5>Arguments:</h5> -<p>The first argument to the '<tt>shr</tt>' instruction must be an <a - href="#t_integer">integer</a> type. The second argument must be an '<tt>ubyte</tt>' -type.</p> +<p>The first argument to the '<tt>lshr</tt>' instruction must be an <a + href="#t_integer">integer</a> type. The second argument must be an '<tt>ubyte</tt>' type.</p> + +<h5>Semantics:</h5> +<p>This instruction always performs a logical shift right operation, regardless +of whether the arguments are unsigned or not. The <tt>var2</tt> most significant +bits will be filled with zero bits after the shift.</p> + +<h5>Example:</h5> +<pre> + <result> = lshr uint 4, ubyte 1 <i>; yields {uint}:result = 2</i> + <result> = lshr int 4, ubyte 2 <i>; yields {uint}:result = 1</i> + <result> = lshr sbyte 4, ubyte 3 <i>; yields {sbyte}:result = 0</i> + <result> = lshr sbyte -2, ubyte 1 <i>; yields {sbyte}:result = 0x7FFFFFFF </i> +</pre> +</div> + +<!-- ======================================================================= --> +<div class="doc_subsubsection"> <a name="i_ashr">'<tt>ashr</tt>' +Instruction</a> </div> +<div class="doc_text"> + +<h5>Syntax:</h5> +<pre> <result> = ashr <ty> <var1>, ubyte <var2> <i>; yields {ty}:result</i> +</pre> + +<h5>Overview:</h5> +<p>The '<tt>ashr</tt>' instruction (arithmetic shift right) returns the first +operand shifted to the right a specified number of bits.</p> + +<h5>Arguments:</h5> +<p>The first argument to the '<tt>ashr</tt>' instruction must be an +<a href="#t_integer">integer</a> type. The second argument must be an +'<tt>ubyte</tt>' type.</p> + <h5>Semantics:</h5> -<p>If the first argument is a <a href="#t_signed">signed</a> type, the -most significant bit is duplicated in the newly free'd bit positions. -If the first argument is unsigned, zero bits shall fill the empty -positions.</p> -<h5>Example:</h5> -<pre> <result> = shr int 4, ubyte %var <i>; yields {int}:result = 4 >> %var</i> - <result> = shr uint 4, ubyte 1 <i>; yields {uint}:result = 2</i> - <result> = shr int 4, ubyte 2 <i>; yields {int}:result = 1</i> - <result> = shr sbyte 4, ubyte 3 <i>; yields {sbyte}:result = 0</i> - <result> = shr sbyte -2, ubyte 1 <i>; yields {sbyte}:result = -1</i> +<p>This instruction always performs an arithmetic shift right operation, +regardless of whether the arguments are signed or not. The <tt>var2</tt> most +significant bits will be filled with the sign bit of <tt>var1</tt>.</p> + +<h5>Example:</h5> +<pre> + <result> = ashr uint 4, ubyte 1 <i>; yields {uint}:result = 2</i> + <result> = ashr int 4, ubyte 2 <i>; yields {int}:result = 1</i> + <result> = ashr ubyte 4, ubyte 3 <i>; yields {ubyte}:result = 0</i> + <result> = ashr sbyte -2, ubyte 1 <i>; yields {sbyte}:result = -1</i> </pre> </div> @@ -4381,7 +4416,7 @@ <a href="mailto:[EMAIL PROTECTED]">Chris Lattner</a><br> <a href="http://llvm.org";>The LLVM Compiler Infrastructure</a><br> - Last modified: $Date: 2006/11/08 01:18:52 $ + Last modified: $Date: 2006/11/08 06:47:32 $ </address> </body> </html> _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
