Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGRRList.cpp updated: 1.18 -> 1.19
SelectionDAG.cpp updated: 1.365 -> 1.366
---
Log message:
silence warning
---
Diffs of the changes: (+0 -50)
ScheduleDAGRRList.cpp | 35 -----------------------------------
SelectionDAG.cpp | 15 ---------------
2 files changed, 50 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.18
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.19
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.18 Thu Nov 2
14:25:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Nov 2 19:28:29 2006
@@ -155,41 +155,6 @@
// Bottom-Up Scheduling
//===----------------------------------------------------------------------===//
-static const TargetRegisterClass *getRegClass(SUnit *SU,
- const TargetInstrInfo *TII,
- const MRegisterInfo *MRI,
- SSARegMap *RegMap) {
- if (SU->Node->isTargetOpcode()) {
- unsigned Opc = SU->Node->getTargetOpcode();
- const TargetInstrDescriptor &II = TII->get(Opc);
- return MRI->getRegClass(II.OpInfo->RegClass);
- } else {
- assert(SU->Node->getOpcode() == ISD::CopyFromReg);
- unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(SrcReg))
- return RegMap->getRegClass(SrcReg);
- else {
- for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
- E = MRI->regclass_end(); I != E; ++I)
- if ((*I)->hasType(SU->Node->getValueType(0)) &&
- (*I)->contains(SrcReg))
- return *I;
- assert(false && "Couldn't find register class for reg copy!");
- }
- return NULL;
- }
-}
-
-static unsigned getNumResults(SUnit *SU) {
- unsigned NumResults = 0;
- for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
- MVT::ValueType VT = SU->Node->getValueType(i);
- if (VT != MVT::Other && VT != MVT::Flag)
- NumResults++;
- }
- return NumResults;
-}
-
/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
/// the Available queue is the count reaches zero. Also update its cycle bound.
void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.365
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.366
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.365 Thu Nov 2
14:25:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 2 19:28:29 2006
@@ -39,15 +39,6 @@
return Res;
}
-// isInvertibleForFree - Return true if there is no cost to emitting the
logical
-// inverse of this node.
-static bool isInvertibleForFree(SDOperand N) {
- if (isa<ConstantSDNode>(N.Val)) return true;
- if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse())
- return true;
- return false;
-}
-
//===----------------------------------------------------------------------===//
// ConstantFPSDNode Class
//===----------------------------------------------------------------------===//
@@ -255,12 +246,6 @@
// SDNode Profile Support
//===----------------------------------------------------------------------===//
-/// getNodeIDOpcode - Return the opcode that has been set for this NodeID.
-///
-static unsigned getNodeIDOpcode(FoldingSetNodeID &ID) {
- return ID.getRawData(0);
-}
-
/// AddNodeIDOpcode - Add the node opcode to the NodeID data.
///
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
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