Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.231 -> 1.232 LegalizeDAG.cpp updated: 1.415 -> 1.416 ScheduleDAGRRList.cpp updated: 1.17 -> 1.18 ScheduleDAGSimple.cpp updated: 1.18 -> 1.19 SelectionDAG.cpp updated: 1.364 -> 1.365 SelectionDAGISel.cpp updated: 1.314 -> 1.315 TargetLowering.cpp updated: 1.78 -> 1.79 --- Log message: For PR786: http://llvm.org/PR786 : Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. --- Diffs of the changes: (+5 -23) DAGCombiner.cpp | 14 +++++--------- LegalizeDAG.cpp | 2 -- ScheduleDAGRRList.cpp | 2 -- ScheduleDAGSimple.cpp | 1 - SelectionDAG.cpp | 1 - SelectionDAGISel.cpp | 6 ------ TargetLowering.cpp | 2 -- 7 files changed, 5 insertions(+), 23 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.231 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.232 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.231 Wed Oct 18 14:08:31 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov 2 14:25:49 2006 @@ -1041,7 +1041,6 @@ ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); MVT::ValueType VT = N1.getValueType(); - unsigned OpSizeInBits = MVT::getSizeInBits(VT); // fold (and c1, c2) -> c1&c2 if (N0C && N1C) @@ -1319,7 +1318,7 @@ /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { if (Op.getOpcode() == ISD::AND) { - if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { + if (isa<ConstantSDNode>(Op.getOperand(1))) { Mask = Op.getOperand(1); Op = Op.getOperand(0); } else { @@ -1856,9 +1855,6 @@ SDOperand N2 = N->getOperand(2); SDOperand N3 = N->getOperand(3); SDOperand N4 = N->getOperand(4); - ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); // fold select_cc lhs, rhs, x, x, cc -> x @@ -1900,7 +1896,7 @@ MVT::ValueType VT = N->getValueType(0); // fold (sext c1) -> c1 - if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) + if (isa<ConstantSDNode>(N0)) return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); // fold (sext (sext x)) -> (sext x) @@ -1958,7 +1954,7 @@ MVT::ValueType VT = N->getValueType(0); // fold (zext c1) -> c1 - if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) + if (isa<ConstantSDNode>(N0)) return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); // fold (zext (zext x)) -> (zext x) // fold (zext (aext x)) -> (zext x) @@ -3578,7 +3574,7 @@ if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { uint64_t C1 = N1C->getValue(); - if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { + if (isa<ConstantSDNode>(N0.Val)) { return DAG.FoldSetCC(VT, N0, N1, Cond); } else { // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an @@ -3806,7 +3802,7 @@ return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); } - if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) { + if (isa<ConstantFPSDNode>(N0.Val)) { // Constant fold or commute setcc. SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); if (O.Val) return O; Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.415 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.416 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.415 Mon Oct 30 20:31:00 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Nov 2 14:25:49 2006 @@ -3690,7 +3690,6 @@ SmallVector<SDOperand, 8> Stores; unsigned TypeByteSize = MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; - unsigned VectorSize = MVT::getSizeInBits(VT)/8; // Store (in the right endianness) the elements to memory. for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { // Ignore undef elements. @@ -4802,7 +4801,6 @@ bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); - bool UseLibCall = true; if (HasMULHS || HasMULHU) { SDOperand LL, LH, RL, RH; ExpandOp(Node->getOperand(0), LL, LH); Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.17 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.18 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.17 Wed Nov 1 16:39:30 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Nov 2 14:25:49 2006 @@ -257,7 +257,6 @@ // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector<SUnit*> NotReady; - SUnit *CurNode = NULL; while (!AvailableQueue->empty()) { SUnit *CurNode = AvailableQueue->pop(); while (CurNode && !isReady(CurNode, CurCycle)) { @@ -373,7 +372,6 @@ // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector<SUnit*> NotReady; - SUnit *CurNode = NULL; while (!AvailableQueue->empty()) { SUnit *CurNode = AvailableQueue->pop(); while (CurNode && !isReady(CurNode, CurCycle)) { Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.18 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.19 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.18 Sun Aug 27 07:54:01 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp Thu Nov 2 14:25:49 2006 @@ -505,7 +505,6 @@ RSLoadStore = 0x0C000000, // Two load store units RSBranch = 0x02000000 // One branch unit }; -static InstrStage CallStage = { CallLatency, RSBranch }; static InstrStage LoadStage = { 5, RSLoadStore }; static InstrStage StoreStage = { 2, RSLoadStore }; static InstrStage IntStage = { 2, RSInteger }; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.364 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.365 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.364 Tue Oct 31 22:48:30 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 2 14:25:49 2006 @@ -1956,7 +1956,6 @@ assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); // Check to see if there is no change. - bool AnyChange = false; if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) return InN; // No operands changed, just return the input node. Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.314 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.315 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.314 Wed Nov 1 19:53:58 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Nov 2 14:25:49 2006 @@ -2343,11 +2343,6 @@ SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other); - // Note, we treat inline asms both with and without side-effects as the same. - // If an inline asm doesn't have side effects and doesn't access memory, we - // could not choose to not chain it. - bool hasSideEffects = IA->hasSideEffects(); - std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); std::vector<MVT::ValueType> ConstraintVTs; @@ -3124,7 +3119,6 @@ static SDOperand getMemsetStringVal(MVT::ValueType VT, SelectionDAG &DAG, TargetLowering &TLI, std::string &Str, unsigned Offset) { - MVT::ValueType CurVT = VT; uint64_t Val = 0; unsigned MSB = getSizeInBits(VT) / 8; if (TLI.isLittleEndian()) Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.78 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.79 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.78 Tue Oct 31 13:40:42 2006 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Nov 2 14:25:49 2006 @@ -504,7 +504,6 @@ } break; case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType VT = Op.getValueType(); MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); // Sign extension. Compute the demanded bits in the result that are not @@ -852,7 +851,6 @@ } return; case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType VT = Op.getValueType(); MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); // Sign extension. Compute the demanded bits in the result that are not _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
