[llvm-commits] [SignlessTypes] CVS: llvm/tools/llvm2cpp/CppWriter.cpp

[Zhou Sheng]

Changes in directory llvm/tools/llvm2cpp:

CppWriter.cpp updated: 1.16.2.3 -> 1.16.2.4
---
Log message:



---
Diffs of the changes:  (+9 -3)

 CppWriter.cpp |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)


Index: llvm/tools/llvm2cpp/CppWriter.cpp
diff -u llvm/tools/llvm2cpp/CppWriter.cpp:1.16.2.3 
llvm/tools/llvm2cpp/CppWriter.cpp:1.16.2.4
--- llvm/tools/llvm2cpp/CppWriter.cpp:1.16.2.3  Sun Oct 22 03:59:01 2006
+++ llvm/tools/llvm2cpp/CppWriter.cpp   Mon Oct 23 13:13:27 2006
@@ -773,10 +773,12 @@
         case Instruction::Add:    Out << "getAdd";  break;
         case Instruction::Sub:    Out << "getSub"; break;
         case Instruction::Mul:    Out << "getMul"; break;
+        case Instruction::URem:   Out << "getURem"; break;
+        case Instruction::SRem:   Out << "getSRem"; break;
+        case Instruction::FRem:   Out << "getFRem"; break;
         case Instruction::UDiv:   Out << "getUDiv"; break;
         case Instruction::SDiv:   Out << "getSDiv"; break;
         case Instruction::FDiv:   Out << "getFDiv"; break;
-        case Instruction::Rem:    Out << "getRem"; break;
         case Instruction::And:    Out << "getAnd"; break;
         case Instruction::Or:     Out << "getOr"; break;
         case Instruction::Xor:    Out << "getXor"; break;
@@ -1023,10 +1025,12 @@
     case Instruction::Add:
     case Instruction::Sub:
     case Instruction::Mul:
+    case Instruction::URem:
+    case Instruction::SRem:
+    case Instruction::FRem:
     case Instruction::UDiv:
     case Instruction::SDiv:
     case Instruction::FDiv:
-    case Instruction::Rem:
     case Instruction::And:
     case Instruction::Or:
     case Instruction::Xor:
@@ -1037,10 +1041,12 @@
         case Instruction::Add: Out << "Instruction::Add"; break;
         case Instruction::Sub: Out << "Instruction::Sub"; break;
         case Instruction::Mul: Out << "Instruction::Mul"; break;
+        case Instruction::URem:Out << "Instruction::URem"; break;
+        case Instruction::SRem:Out << "Instruction::SRem"; break;
+        case Instruction::FRem:Out << "Instruction::FRem"; break;
         case Instruction::UDiv:Out << "Instruction::UDiv"; break;
         case Instruction::SDiv:Out << "Instruction::SDiv"; break;
         case Instruction::FDiv:Out << "Instruction::FDiv"; break;
-        case Instruction::Rem: Out << "Instruction::Rem"; break;
         case Instruction::And: Out << "Instruction::And"; break;
         case Instruction::Or:  Out << "Instruction::Or";  break;
         case Instruction::Xor: Out << "Instruction::Xor"; break;



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