Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.11 -> 1.12
ARMISelDAGToDAG.cpp updated: 1.33 -> 1.34
ARMInstrInfo.td updated: 1.18 -> 1.19
---
Log message:
initial support for branches
---
Diffs of the changes: (+30 -3)
ARMAsmPrinter.cpp | 3 +--
ARMISelDAGToDAG.cpp | 21 ++++++++++++++++++++-
ARMInstrInfo.td | 9 +++++++++
3 files changed, 30 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.11
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.12
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.11 Thu Aug 17 12:09:40 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp Thu Aug 24 08:45:54 2006
@@ -174,8 +174,7 @@
O << "#" << (int)MO.getImmedValue();
break;
case MachineOperand::MO_MachineBasicBlock:
- assert(0 && "not implemented");
- abort();
+ printBasicBlockLabel(MO.getMachineBasicBlock());
return;
case MachineOperand::MO_GlobalAddress: {
GlobalValue *GV = MO.getGlobal();
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.33
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.34
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.33 Mon Aug 21 17:00:32 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Aug 24 08:45:54 2006
@@ -53,6 +53,7 @@
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setSchedulingPreference(SchedulingForRegPressure);
computeRegisterProperties();
@@ -71,7 +72,9 @@
CMP,
- SELECT
+ SELECT,
+
+ BR
};
}
}
@@ -83,6 +86,7 @@
case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
case ARMISD::SELECT: return "ARMISD::SELECT";
case ARMISD::CMP: return "ARMISD::CMP";
+ case ARMISD::BR: return "ARMISD::BR";
}
}
@@ -312,6 +316,19 @@
return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
}
+static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
+ SDOperand Chain = Op.getOperand(0);
+ ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
+ SDOperand LHS = Op.getOperand(2);
+ SDOperand RHS = Op.getOperand(3);
+ SDOperand Dest = Op.getOperand(4);
+
+ assert(CC == ISD::SETNE);
+
+ SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
+ return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, Cmp);
+}
+
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default:
@@ -329,6 +346,8 @@
return LowerRET(Op, DAG);
case ISD::SELECT_CC:
return LowerSELECT_CC(Op, DAG);
+ case ISD::BR_CC:
+ return LowerBR_CC(Op, DAG);
}
}
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.18
llvm/lib/Target/ARM/ARMInstrInfo.td:1.19
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.18 Mon Aug 21 17:00:32 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Thu Aug 24 08:45:55 2006
@@ -37,6 +37,8 @@
let Pattern = pattern;
}
+def brtarget : Operand<OtherVT>;
+
def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
[SDNPHasChain, SDNPOutFlag]>;
@@ -50,6 +52,9 @@
[SDNPHasChain, SDNPOptInFlag]>;
def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag,
SDNPOutFlag]>;
+def SDTarmbr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
+def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain,
SDNPInFlag]>;
+
def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
@@ -107,6 +112,10 @@
[(set IntRegs:$dst, (armselect IntRegs:$true,
IntRegs:$false))]>;
}
+def bne : InstARM<(ops brtarget:$dst),
+ "bne $dst",
+ [(armbr bb:$dst)]>;
+
def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
"cmp $a, $b",
[(armcmp IntRegs:$a, IntRegs:$b)]>;
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