Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGISel.h updated: 1.23 -> 1.24
---
Log message:
Move DAGSize to SelectionDAGISel; it's used in tablegen'd isel code.
---
Diffs of the changes: (+7 -2)
SelectionDAGISel.h | 9 +++++++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.23
llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.24
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.23 Tue Aug 1 14:14:14 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h Mon Aug 7 17:16:08 2006
@@ -17,10 +17,10 @@
#include "llvm/Pass.h"
#include "llvm/Constant.h"
+#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
namespace llvm {
- class SelectionDAG;
class SelectionDAGLowering;
class SDOperand;
class SSARegMap;
@@ -39,8 +39,10 @@
SSARegMap *RegMap;
SelectionDAG *CurDAG;
MachineBasicBlock *BB;
+ std::vector<SDNode*> TopOrder;
+ unsigned DAGSize;
- SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
+ SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0), JT(0,0,0,0) {}
TargetLowering &getTargetLowering() { return TLI; }
@@ -52,6 +54,9 @@
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
+ virtual void SelectRootInit() {
+ DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
+ }
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// addressing mode, according to the specified constraint code. If this
does
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