Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGSimple.cpp updated: 1.16 -> 1.17 --- Log message: Copy the liveins for the first block. PR859: http://llvm.org/PR859 --- Diffs of the changes: (+14 -0) ScheduleDAGSimple.cpp | 14 ++++++++++++++ 1 files changed, 14 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.16 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.17 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.16 Wed Aug 2 07:30:23 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp Thu Aug 3 15:51:06 2006 @@ -14,9 +14,11 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "sched" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -669,6 +671,18 @@ /// EmitAll - Emit all nodes in schedule sorted order. /// void ScheduleDAGSimple::EmitAll() { + // If this is the first basic block in the function, and if it has live ins + // that need to be copied into vregs, emit the copies into the top of the + // block before emitting the code for the block. + MachineFunction &MF = DAG.getMachineFunction(); + if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) { + for (MachineFunction::livein_iterator LI = MF.livein_begin(), + E = MF.livein_end(); LI != E; ++LI) + if (LI->second) + MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, + LI->first, RegMap->getRegClass(LI->second)); + } + std::map<SDNode*, unsigned> VRBaseMap; // For each node in the ordering _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
