Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.264 -> 1.265
---
Log message:
Now that the ISel is available, it's possible to create a default instruction
scheduler creator.
---
Diffs of the changes: (+22 -17)
SelectionDAGISel.cpp | 39 ++++++++++++++++++++++-----------------
1 files changed, 22 insertions(+), 17 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.264
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.265
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.264 Tue Aug 1
13:29:48 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 1 14:14:14 2006
@@ -68,7 +68,8 @@
cl::desc("Instruction schedulers available:"));
static RegisterScheduler
- defaultListDAGScheduler("default", " Best scheduler for the target", NULL);
+ defaultListDAGScheduler("default", " Best scheduler for the target",
+ createDefaultScheduler);
} // namespace
namespace {
@@ -124,6 +125,24 @@
namespace llvm {
//===--------------------------------------------------------------------===//
+ /// createDefaultScheduler - This creates an instruction scheduler
appropriate
+ /// for the target.
+ ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
+ MachineBasicBlock *BB) {
+ TargetLowering &TLI = IS->getTargetLowering();
+
+ if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
{
+ return createTDListDAGScheduler(IS, DAG, BB);
+ } else {
+ assert(TLI.getSchedulingPreference() ==
+ TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
+ return createBURRListDAGScheduler(IS, DAG, BB);
+ }
+ }
+
+
+
//===--------------------------------------------------------------------===//
/// FunctionLoweringInfo - This contains information that is global to a
/// function that is used when lowering a region of the function.
class FunctionLoweringInfo {
@@ -3614,22 +3633,8 @@
RegisterScheduler::getDefault();
if (!Ctor) {
- if (std::string("default") == std::string(ISHeuristic)) {
- if (TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForLatency)
- Ctor = RegisterScheduler::FindCtor("list-td");
- else {
- assert(TLI.getSchedulingPreference() ==
- TargetLowering::SchedulingForRegPressure && "Unknown sched
type!");
- Ctor = RegisterScheduler::FindCtor("list-burr");
- }
-
- assert(Ctor && "Default instruction scheduler not present");
- if (!Ctor) Ctor = RegisterScheduler::FindCtor("none");
- } else {
- Ctor = RegisterScheduler::FindCtor(ISHeuristic);
- }
-
- RegisterScheduler::setDefault(Ctor);
+ Ctor = RegisterScheduler::FindCtor(ISHeuristic);
+ RegisterScheduler::setDefault(Ctor);
}
assert(Ctor && "No instruction scheduler found");
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