Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.279 -> 1.280 X86InstrMMX.td updated: 1.12 -> 1.13 --- Log message: INC / DEC instructions have shorter code size than ADD32ri8, etc. --- Diffs of the changes: (+13 -7) X86InstrInfo.td | 16 ++++++++++++---- X86InstrMMX.td | 4 +--- 2 files changed, 13 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.279 llvm/lib/Target/X86/X86InstrInfo.td:1.280 --- llvm/lib/Target/X86/X86InstrInfo.td:1.279 Tue Jul 11 14:49:49 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Tue Jul 18 19:27:29 2006 @@ -314,18 +314,22 @@ class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> : X86Inst<o, f, NoImm, ops, asm> { let Pattern = pattern; + let CodeSize = 3; } class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> : X86Inst<o, f, Imm8 , ops, asm> { let Pattern = pattern; + let CodeSize = 3; } class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> : X86Inst<o, f, Imm16, ops, asm> { let Pattern = pattern; + let CodeSize = 3; } class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> : X86Inst<o, f, Imm32, ops, asm> { let Pattern = pattern; + let CodeSize = 3; } //===----------------------------------------------------------------------===// @@ -1060,6 +1064,7 @@ // unary instructions +let CodeSize = 2 in { def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst", [(set GR8:$dst, (ineg GR8:$src))]>; def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst", @@ -1090,17 +1095,19 @@ def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", [(store (not (loadi32 addr:$dst)), addr:$dst)]>; } +} // CodeSize // TODO: inc/dec is slow for P4, but fast for Pentium-M. +let CodeSize = 2 in def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", [(set GR8:$dst, (add GR8:$src, 1))]>; -let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst", [(set GR16:$dst, (add GR16:$src, 1))]>, OpSize; def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst", [(set GR32:$dst, (add GR32:$src, 1))]>; } -let isTwoAddress = 0 in { +let isTwoAddress = 0, CodeSize = 2 in { def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", @@ -1109,16 +1116,17 @@ [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; } +let CodeSize = 2 in def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst", [(set GR8:$dst, (add GR8:$src, -1))]>; -let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst", [(set GR16:$dst, (add GR16:$src, -1))]>, OpSize; def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst", [(set GR32:$dst, (add GR32:$src, -1))]>; } -let isTwoAddress = 0 in { +let isTwoAddress = 0, CodeSize = 2 in { def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.12 llvm/lib/Target/X86/X86InstrMMX.td:1.13 --- llvm/lib/Target/X86/X86InstrMMX.td:1.12 Tue May 16 02:21:53 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Jul 18 19:27:29 2006 @@ -22,9 +22,7 @@ class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasMMX]> { - let Pattern = pattern; -} + : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>; // Some 'special' instructions def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst), _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits