[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.cpp ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.12 -> 1.13
ARMInstrInfo.cpp updated: 1.2 -> 1.3
ARMRegisterInfo.cpp updated: 1.4 -> 1.5
---
Log message:

handle the "mov reg1, reg2" case in isMoveInstr



---
Diffs of the changes:  (+20 -6)

 ARMISelDAGToDAG.cpp |   10 ++++++----
 ARMInstrInfo.cpp    |   14 +++++++++++++-
 ARMRegisterInfo.cpp |    2 +-
 3 files changed, 20 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.12 
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.13
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.12        Mon Jun 12 07:28:08 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp     Tue Jun 27 16:52:45 2006
@@ -183,10 +183,12 @@
   ScheduleAndEmitDAG(DAG);
 }
 
-static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode 
*N) {
+static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode 
*N, SDOperand Op) {
   int FI = cast<FrameIndexSDNode>(N)->getIndex();
-  Result = CurDAG->SelectNodeTo(N, ARM::movrr, MVT::i32,
-                               CurDAG->getTargetFrameIndex(FI, MVT::i32));
+
+  SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
+
+  Result = CurDAG->SelectNodeTo(N, ARM::movri, Op.getValueType(), TFI);
 }
 
 void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
@@ -198,7 +200,7 @@
     break;
 
   case ISD::FrameIndex:
-    SelectFrameIndex(CurDAG, Result, N);
+    SelectFrameIndex(CurDAG, Result, N, Op);
     break;
   }
 }


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.2 
llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.3
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.2    Mon May 22 21:48:20 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp        Tue Jun 27 16:52:45 2006
@@ -27,7 +27,19 @@
 ///
 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
                                  unsigned &SrcReg, unsigned &DstReg) const {
-  return false;
+  MachineOpCode oc = MI.getOpcode();
+  switch (oc) {
+  default:
+    return false;
+  case ARM::movrr:
+    assert(MI.getNumOperands() == 2 &&
+          MI.getOperand(0).isRegister() &&
+          MI.getOperand(1).isRegister() &&
+          "Invalid ARM MOV instruction");
+    SrcReg = MI.getOperand(1).getReg();;
+    DstReg = MI.getOperand(0).getReg();;
+    return true;
+  }
 }
 
 /// isLoadFromStackSlot - If the specified machine instruction is a direct


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.4 
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.5
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.4 Sat Jun 17 19:08:07 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp     Tue Jun 27 16:52:45 2006
@@ -81,7 +81,7 @@
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
 
-  assert (MI.getOpcode() == ARM::movrr);
+  assert (MI.getOpcode() == ARM::movri);
 
   unsigned FrameIdx = 1;
 



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