Changes in directory llvm/lib/Target/Alpha:
AlphaAsmPrinter.cpp updated: 1.44 -> 1.45
AlphaISelDAGToDAG.cpp updated: 1.45 -> 1.46
AlphaISelLowering.cpp updated: 1.53 -> 1.54
---
Log message:
Add memory operand and int regs
---
Diffs of the changes: (+46 -0)
AlphaAsmPrinter.cpp | 14 ++++++++++++++
AlphaISelDAGToDAG.cpp | 18 ++++++++++++++++++
AlphaISelLowering.cpp | 14 ++++++++++++++
3 files changed, 46 insertions(+)
Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.44
llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.45
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.44 Wed Jun 21 08:37:27 2006
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed Jun 21 10:42:36 2006
@@ -62,6 +62,10 @@
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode);
+ bool PrintAsmMemoryOperand(const MachineInstr *MI,
+ unsigned OpNo,
+ unsigned AsmVariant,
+ const char *ExtraCode);
};
} // end of anonymous namespace
@@ -277,3 +281,13 @@
printOperand(MI, OpNo);
return false;
}
+
+bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+ unsigned OpNo,
+ unsigned AsmVariant,
+ const char *ExtraCode) {
+ if (ExtraCode && ExtraCode[0])
+ return true; // Unknown modifier.
+ printOperand(MI, OpNo);
+ return false;
+}
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.45
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.46
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.45 Tue Jun 13 15:34:47 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Jun 21 10:42:36 2006
@@ -119,6 +119,24 @@
return "Alpha DAG->DAG Pattern Instruction Selection";
}
+ /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+ /// inline asm expressions.
+ virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ char ConstraintCode,
+ std::vector<SDOperand> &OutOps,
+ SelectionDAG &DAG) {
+ SDOperand Op0;
+ switch (ConstraintCode) {
+ default: return true;
+ case 'm': // memory
+ Select(Op0, Op);
+ break;
+ }
+
+ OutOps.push_back(Op0);
+ return false;
+ }
+
// Include the pieces autogenerated from the target description.
#include "AlphaGenDAGISel.inc"
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.53
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.54
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.53 Wed Jun 21 08:37:27 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 21 10:42:36 2006
@@ -591,6 +591,7 @@
switch (ConstraintLetter) {
default: break;
case 'f':
+ case 'r':
return C_RegisterClass;
}
return TargetLowering::getConstraintType(ConstraintLetter);
@@ -614,6 +615,19 @@
Alpha::F24, Alpha::F25, Alpha::F26,
Alpha::F27, Alpha::F28, Alpha::F29,
Alpha::F30, Alpha::F31, 0);
+ case 'r':
+ return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
+ Alpha::R3 , Alpha::R4 , Alpha::R5 ,
+ Alpha::R6 , Alpha::R7 , Alpha::R8 ,
+ Alpha::R9 , Alpha::R10, Alpha::R11,
+ Alpha::R12, Alpha::R13, Alpha::R14,
+ Alpha::R15, Alpha::R16, Alpha::R17,
+ Alpha::R18, Alpha::R19, Alpha::R20,
+ Alpha::R21, Alpha::R22, Alpha::R23,
+ Alpha::R24, Alpha::R25, Alpha::R26,
+ Alpha::R27, Alpha::R28, Alpha::R29,
+ Alpha::R30, Alpha::R31, 0);
+
}
}
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